SiTime Targets AI with Integrated Clock Chip for Data Centers
A new family of high-performance clock devices developed by SiTime is specifically adapted for the AI era. The Chorus chip integrates the clock generator, resonator, and oscillator in the same package, creating what the Santa Clara, Calif.-based company calls a multi-output clock-system-on-chip (ClkSoC).
By bringing all of these building blocks together instead of keeping them apart, SiTime said the MEMS timing devices deliver up to 10X more precision to data centers. They also require 50% less real estate.
In any system, the resonator is the source of all timing signals. It outputs a frequency that acts as the heartbeat of a system or network to make sure the servers, switches, and all other building blocks of the data center stay on schedule. SiTime said Chorus differs from traditional clock devices by integrating a timing device based on its MEMS technology. Importantly, it’s designed to thrive in the heat and other harsh conditions in data centers.
“Before Chorus, hardware designers had to use discrete product types, such as clocks, oscillators, and resonators, which resulted in performance compromises,” said Piyush Sevalia, SiTime’s VP of marketing.
What’s the driving force behind the new approach? The cloud and other technology giants pushing the envelope in AI technology are bundling together tens of thousands of AI chips in data centers to train more advanced types of AI, including large language models (LLMs). In turn, all of these chips must communicate with each other within the same server, the same column of servers, and the overarching network faster than ever. This inevitably drives up demand for high-bandwidth, low-latency connectivity.
While the AI chips are slinging data between each other and memory as fast as possible, they frequently must ferry data between several different clock domains. Timing devices make sure that none of the chips in the system—from the CPU to the AI accelerators coordinating with it and with other AI chips on the same network—are racing ahead or falling behind each other. It’s a feature called “clock synchronization.” The upshot, said SiTime, is robust and accurate timing becomes even more vital.
The tradeoff is that data centers are full of timing devices. Every networking interface card (NIC) can have one to three timing devices, while a single switch can be equipped with as many as 24.
MEMS: A New Approach to Timing in Data Centers
SiTime hopes to bring high-performance timing into the future with its silicon MEMS technology.
While quartz timing devices have been the industry standard for decades, SiTime said the technology is reaching its limits in areas ranging from aerospace and automotive to the worlds of wired and wireless connectivity. According to the company, its MEMS-based timing devices have been gaining ground due to the higher accuracy, reliability, and stability of the underlying silicon. For example, Tesla uses SiTime’s timing chips in its Dojo supercomputer.
In terms of reliability, MEMS is also a winner. SiTime said its chips are less susceptible to temperature, vibrations, shock, and electromagnetic interference (EMI) that can all pose a threat to timing signals. The core advantage of MEMS is that it’s manufactured the same way as other silicon chips.
Thus, SiTime can integrate them more easily with other components in a single chip. Such is the case with the Chorus family, which simplifies the system’s clock architecture by removing the need for a separate timing reference.
The Chorus clock generators include the resonator that acts as the timing reference, the oscillator that outputs the frequency of the clock signals, and programmable phase-locked loop (PLL) to manipulate the frequency of the signals. In addition, on-chip NVM memory handles different configurations of the clock tree, which is the clock distribution network within a system. The first chips in the family—the SiT91211 and the SiT91213—come in compact 4 × 4-mm QFN packages.
The result is that a single Chorus timing chip can deliver up to four differential clock outputs or up to eight single-ended LVCMOS outputs, replacing up to four oscillators at once. These outputs are all fully programmable, each with a dedicated power supply.
SiTime said it makes sense to use Chorus clock devices in situations where it’s necessary to coordinate several different SoCs arranged on the same circuit board. Instead of driving every SoC with a separate oscillator on the PCB, a single Chorus chip can route the clock signals to several processors simultaneously, replacing up to four oscillators. The space savings can total up to 50% for the full clock tree. Chorus also supports clock synchronization because all of the timing signals spring from the same PLL.
In data centers, clock generators are mostly paired with a separate resonator or oscillator to supply the input clock reference that coordinates everything in the system. But as the timing signal travels over the PCB to the clock device, it can be exposed to electrical noise that can throw off the system. As more AI silicon is piled into the data center, it’s becoming more of a challenge to pinpoint a “quiet” spot in the system where you can safely place the timing devices.
This isn’t the only drawback with traditional clock devices, said SiTime. The impedance of the timing source must also match the impedance of the clock IC attached to it as well as the other clocks in a system.
By integrating all of the necessary timing devices into a single chip, SiTime claims Chorus can solve these problems, reducing its exposure to system noise along with component count and circuit complexity.
MEMS Clock ICs: More Precision, More Flexibility
Flexibility is one of the focal points of the new Chorus clock devices, which are currently sampling to early customers.
The chips have a flexible programmable frequency range of 1 to 700 MHz along with output voltages of 1.8, 2.5, to 3.3 V, so its customers can adapt them to different scenarios. They incorporate I2C and SPI interfaces for control and communication, and the devices can be configured even after they’re embedded in the data center by adding a new configuration to the on-chip memory.
To handle the huge quantities of data entering their data centers, cloud and other technology leaders are upgrading to Ethernet that runs at 400 Gb/s, with data rates of 800 Gb/s and 1.6 Tb/s close behind it. The PCIe bus, the most widely used high-speed serial interconnect in the data center, is also doubling its data rate to 32 GT/s with PCIe Gen 5, and PCIe Gen 6 will see data rates double to 64 GT/s. As a result, timing requirements for AI in terms of the jitter, drift, and other metrics are becoming tighter over time.
Featuring 70 fs of RMS phase jitter, SiTime said the flagship chip in the family can hang with the high-bandwidth networks, usually based on Ethernet, weaving throughout the data center. The other clock device in the family, which features 150 fs of jitter, is well-suited for PCIe and other data interconnects that bridge gaps between chips instead of between servers and switches.
SiTime said the Chorus clock ICs are also highly robust against environmental disturbances. This includes sudden changes in the amount of heat in a system, which can impact the stability of the timing signals.
Another key feature is frequency stability of ±20 ppm and ±50 ppm over the full operating temperature range of –40 to 105°C. These devices are also resistant to shock and vibration and offer EMI reduction thanks to their configurable spread-spectrum clock generation. They have a high degree of power-supply noise rejection (PSNR) to prevent noise from negatively impacting the frequency of the timing signals in a system.
With the Chorus announcement, SiTime said it can cover every type of timing device used in the data center. Chorus complements its Epoch family of oven-controlled oscillators (OCXOs) released last year.
Broader availability of the Chorus family is expected in the second half of 2024.
