Addressing Digital and Analog Integration at the Chip Level
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What you’ll learn
- Details about Agile Analog’s IP products.
- How the IP products are created.
- What types of IP are available?
The world is analog, and computer logic is (currently) digital, so being able to convert from one to the other in an optimal manner is critical to a good chip design. Providing a solution for digital and analog integration at the chip level, Agile Analog’s IP products can support a range of on-chip functionality, from sensing and security to power management and data conversion.
These configurable IP products are provided as fab-ready IP, optimized for each individual application, foundry, and node. We talk to Chris Morrison, Director of Product Marketing at Agile Analog, about the issues involved in IP integration at the chip level.
The company developed an automated method that configures platform IP for any supported process, from legacy nodes like 180 nm, up to the latest processes. It offers the ability to choose the appropriate foundry and node, regardless of IP product. Agile Analog provides a comprehensive set of deliverables, enabling the simulation, test, validation, and integration of IP with minimal effort.
Agile built a process to generate customizable analog IP using an automated program called Composa, which automatically generates analog IP. This approach creates bespoke and verified analog IP solutions that shrink time-to-market while reducing risk and increasing performance. It uses established and tested analog IP circuits from the Composa library, for a design-once and reuse many times model.
Composa can also regenerate the analog IP solution for a different process technology. This is useful when switching to a different foundry or shrinking the chip to suit a smaller node. Presented as the first, automatically generated, process-agnostic analog IP, it addresses the issue of analog IP cores that need re-engineering to suit different silicon process technologies.
Another advantage to Composa is that it offers a simpler process to integrate analog functions onto the chip, rather than resorting to discrete analog components. As a result, it reduces complexity, overall motherboard size, BOM, and risk.
