Communications: Timing Chips Take On Tight Margins In Sonet SDH And PDH Systems

Aug. 9, 2004

Sonet/SDH and plesiochronous digital hierarchy (PDH) systems can take advantage of a timing-chip duo to achieve exceptional performance. The ZL30106 digital phase-locked loop (PLL) offers an OC-3 jitter compliance margin of 20 ps rms and features hitless reference switching, reference monitoring, and holdover. It accepts three input references, provides a range of output clocks, and achieves a holdover frequency accuracy of 0.01 ppm. The ZL30416 analog PLL performs jitter attenuation and rate conversion for Sonet/SDH equipment. It meets the requirements of line-card applications from OC-3/STM-1 up to OC-192/STM-64 transmission rates. Ultra-low-jitter output clocks meet Telcordia GR-253-CORE jitter specifications up to OC-192. Available in a 64-lead TQFP, the ZL30106 sells for $15 each in 1000-unit lots. The ZL30416 APLL, housed in a 64-contact CBGA, is priced at $36.19 each in 1000-unit quantities.

Zarlink Semiconductor Inc.http://products.zarlink.com/product_profiles/ZL30106, and
http://products.zarlink.com/product_profiles/ZL30416

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.