IC Verification Tool Tackles Blurring Lines Between Analog and Digital

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Siemens EDA unveiled a new mixed-signal verification tool that chip designers can use to evaluate systems-on-chip (SoCs) used everywhere from data centers to 5G networks to cars to IoT devices.

Symphony Pro, as Siemens portrays it, is a state-of-the-art platform that aims to upend the status quo in mixed-signal verification, offering productivity gains of up to 10X. The tool includes a comprehensive and intuitive visual debug cockpit that promises to make it much easier for chip makers to find and fix bugs in mixed-signal designs, which are some of the most intricate and high-speed portions of chips.

Symphony Pro is an advanced tier of its Symphony platform, which when it launched in 2018 promised a speedup of up to 5X compared to existing solutions. It has been a hit, with more than 100 customers employing the electronic-design-automation (EDA) tool to tape out about 80 chips to date.

What sets apart Symphony Pro, which is based on the company’s Analog Fast SPICE (AFS) technology, is it taps more robust and automated digital verification technologies to boost productivity for chip engineers.

Sumit Vishwakarma, principal product manager in Siemens' mixed-signal unit, said with Symphony Pro it is trying to stay in step with chip companies rapidly pushing the envelope in mixed-signal architectures, which is inevitably leading to additional complexity for chip makers.

As a result, bugs are increasingly slipping through their fingers, derailing chip designs and increasing time to market. Against that backdrop, companies need faster, more accurate, and easy-to-use software that can verify the connectivity, functionality, and performance of mixed-signal circuitry.

Blurring Boundaries

Siemens EDA hopes to turn heads with Symphony Pro at a time when engineers are packing more advanced analog IP into their chip designs. Around 85% of all chip design starts are now mixed-signal, according to IBS Research.

“We keep hearing that we live in a digital world,” said Vishwakarma. “But the world around us is analog. And so, what we actually live in is a mixed-signal world where digital and analog are working together."

Analog IP is increasingly ubiquitous in modern chips, whether it is integrating the analog signal chain with digital signal processors in 5G massive-MIMO radios or the digital RF-sampling data converters in radar. There are also switch chips that feed data to processors in the data center via high-speed SerDes. Moreover, chip makers are rolling out networking chips for factory floors with Ethernet PHYs inside.

The technology is set to become even more important as the likes of AMD and Intel move into the era of chiplets, slicing chips into smaller, modular building blocks that are then bundled in a larger package.

“The concept behind a chiplet is divide and conquer,” noted Vishwakarma. And as even the world's most advanced chips struggle to stay on track with Moore's Law, “we have start thinking outside the box.”

When you disaggregate a larger processor into chiplets, you must guarantee that they can talk to each other almost as fast as they would sharing the same die. To do that, companies use SerDes, which is the cornerstone of high-speed serial interconnects, ranging from the PCIe standard to NVIDIA’s NvLink, and the UCIe die-to-die chiplet standard backed by Arm, Google, Intel, Microsoft, TSMC, and others.

“Where there's a chiplet, there's mixed-signal,” said Vishwakarma.

Playing Catch-Up

With the lines between analog and digital blurring in modern chips, companies are looking for tools that can rise to the challenge, said Vishwakarma.

Mixed-signal verification is a challenging task because before you can test that everything on the chip works, you have to run simulations on both the analog and digital portions of the design. But using a single verification platform to model both the digital and analog domains is a tall order. 

“In the digital domain, there is a lot of innovation happening with new digital verification technologies. This makes the infrastructure very reusable and scalable, which means once you build the test bench, you can apply it to any other device,” he said. But analog verification has had a hard time keeping up.

What it wanted to accomplish with Symphony was the ability to combine the company's leading AFS technology with any digital simulator on the market, from Cadence's Xcelium to Siemens EDA's Questa. 

It was designed to address a lot of the limitations engineers face when verifying mixed-signal designs. Siemens is hoping to further bridge the gap between analog and digital with Symphony Pro.

Symphony Pro brings to the analog and mixed-signal table a host of advanced digital verification tools, including the industry-standard Universal Verification Methodology (UVM), which offers fast simulation in a unified environment for higher throughput and capacity. The fact that it can support the Unified Power Format (UPF) means engineers can also verify chip designs through the prism of power consumption.

There are tradeoffs, however. Symphony Pro is only compatible with Siemens EDA's digital solvers.

Visual Learning

Debugging is a part of the verification process that's still a challenge when it comes to mixed-signal. The intricacies of mixed-signal ICs mean engineers have to painstakingly review reams of waveforms, schematics, and other data by hand to check for problems. Thus, they have to rely on their knowledge, intuition, and lots of trial and error to figure out what's wrong with IC designs that refuse to cooperate.

To reduce the time it takes to find and fix bugs, Symphony Pro comes with a debug environment called Visualizer MS. It promises to save engineers many headaches by offering more extensive analysis and automation capabilities.

What sets Symphony Pro apart from other software tools on the market is that it creates an abstract representation of a chip design and then generates a database of virtually anything you need to know about it. That includes information on digital blocks—in the form of Verilog and SystemVerilog—and details on the analog blocks down to the transistor level, as well as the analog and digital waveforms.

The software feeds all of the information into the Visualizer MS Debug environment, which opens several windows that let engineers easily navigate and examine a design from different points of view.

"You get a very comprehensive view of your mixed-signal design," said Vishwakarma, making it easier to pinpoint weak points in designs, reducing the time it takes to troubleshoot flaws.

Included are the "Design Window," which shows the full mixed-signal hierarchy, with color coding for different simulation languages, and "Source Window" that displays source code for different blocks in Spice and HDL. Other windows show the underlying schematics of the transistors and the many connections at the boundaries between analog and digital blocks, where problems tend to pile up.

One of its most advanced bug-spotting features is called "Logic Cone," which digs into the vast amounts of simulation data to locate the source or "driver" of a specific problem in a design, said Vishwakarma. 

One early customer of the Symphony Pro platform is Silicon Labs. The company used the software to reduce the time it takes to verify its chips for the IoT market from days to hours. 

Check out videos and other coverage from DAC 2022.