This article is part of the TechXchange: Addressing Chip Verification Challenges
Cadence rolled out its latest AI-powered electronic design automation (EDA) platform called Verisium, which promises to ease the amount of time and resources that chipmakers put into the verification process.
The Santa Clara, California-based company said MediaTek and Samsung are among the first companies using Verisium to identify bugs in system-on-chip (SoC) designs and diagnose what’s causing things to go wrong.
Modern processors are comprised of billions of transistors that must fit into squares of silicon as small as a fingernail. How everything is arranged on the chip and how (and where) it’s placed within a system impacts metrics like performance, power efficiency, and even cost. As a result, Cadence has started adding AI to its software tools to automate more aspects of the IC design process.
Verisium is a complement to its Cerebrus Intelligent Chip Explorer platform for AI-enhanced implementation and Optimality Intelligent System Explorer for AI-powered system-level analysis.
A Painstaking Process
The purpose of verification is to identify and resolve chip design defects in a pre-manufactured state. It’s the end-stage process of testing the quality of the design and that everything inside works as planned in a product.
The verification process usually starts after you complete the chip design. The hardware is simulated with software code in a hardware description language (HDL) used to test the various building blocks of the SoC. The test bench effectively creates a virtual version of the SoC that can be supplied with signals. Subsequently, you can measure and evaluate the responses from the SoC to figure out whether the SoC or IP inside has any issues.
Cadence said Verisium works with its existing verification engines: Palladium for emulation, Protium for prototyping, Xcelium for simulation, Jasper for formal verification, and its Helium virtual and hybrid studios.
Previously, you would have to run every one of these engines separately for every step in the verification process—what Cadence calls “a single-run, single-engine” approach. Verisium, on the other hand, leverages big data and AI to optimize multiple runs of multiple engines over the full SoC design and verification campaign.
As SoC complexity continues to rise, the verification process tends to take more time and resources than any other silicon engineering task. And so, as Cadence tells it, verification is ripe for improvement using AI.
Verisium also runs on top of Cadence’s new “JedAI” platform, which pools vast quantities of data stemming from the chip design process, analyzes it to identify areas of improvement, and even stores it for future use.
Cadence said JedAI is a platform in the sense that its AI-powered offerings—Verisium, Cerebrus, and Optimality—and third-party silicon lifecycle management systems sit on top of it. When it comes to using Verisium, its verification tools feed data stemming from the verification process, ranging from waveforms, coverage, and reports to log files, into the JedAI platform, where it’s all stored and evaluated.
Then, JedAI builds machine-learning models and mines other proprietary metrics from the data, sharing what it learns with the company’s Verisium to identify potential areas of improvement or root-cause issues.
“As chip design size and complexity has increased exponentially over the past decade, the volume of design and verification data has also increased with it,” said Venkat Thanvantri, Cadence’s VP of AI R&D. “Previously, we saw that once a chip design project was completed, the valuable data was deleted to make way for the next project. There are valuable learnings in the legacy data, and the Cadence JedAI Platform makes it easy for engineering teams to access these learnings and apply them to future designs.”
Starter Apps
Customers can get started with several apps when they use Verisium. Some of them tap into machine learning, both supervised and unsupervised, including reinforcement learning, while others don’t.
- Verisium AutoTriage: Builds machine-learning models that help automate the repetitive task of sorting through failures to find the worst ones. To do so, it predicts and classifies test failures with common root causes.
- Verisium SemanticDiff: Uses algorithms to compare source-code revisions of IP building blocks or the full SoCs. The app classifies these revisions and ranks those that are the most disruptive to the system's behavior to help pinpoint potential bug hotspots.
- Verisium WaveMiner: Applies AI engines to analyze waveforms from multiple verification runs and determine which signals, at which times, are most likely to represent the root cause of a test failure.
- Verisium PinDown: Integrates with the Cadence JedAI Platform and other industry-standard tools to build machine-learning models of source-code changes, test reports, and log files to predict the source-code check-ins that are most likely to have introduced failures.
- Verisium Debug: Natively integrated with the JedAI Platform and other Verisium apps, this app uses AI for the purposes of root-cause analysis, along with support for the simultaneous and automatic comparison of passing and failing tests. The debug solution spans from IP to SoC and from single-run to multi-run verification.
- Verisium Manager: Brings Cadence’s full IP and SoC-level verification management solution with verification planning, job scheduling, and multi-engine coverage onto its JedAI platform. It uses AI technologies to improve how efficiently data centers run verification. This app integrates directly with Cadence’s other Verisium apps, opening the door for pushbutton deployment of the complete Verisium platform from a unified browser-based management console.
AI Time Saver
Paul Cunningham, senior vice president and general manager of Cadence’s system and verification division, said Verisium would help chip companies make more informed decisions during the design and verification process. But the biggest impact is apparently on the productivity side of things.
The company said its customers are already using Verisium to triage failing tests more than 3X faster than they could previously, with reductions in the time it takes to determine the root-cause failure by up to 75%.
Given that failure analysis and debug represent 50% (or in some cases more) of the time chip firms devote on verification, Cadence claimed the AI-driven Verisium tool could result in major improvements in productivity.
