RTL Design Tool Brings Gains in Productivity, Quality of Results
This article appeared in Microwaves & RF and has been published here with permission.
This article is part of our Design Automation Conference 2023 coverage.
The Overview
In its new Joules RTL Design Studio tool, Cadence Design Systems aims to provide users with information that will lead to a speedier register-transfer-level (RTL) design and implementation process. Through a single, unified cockpit, it affords front-end designers access to digital design analysis and debugging capabilities, from which they can attain a fully optimized RTL design before handing it off to implementation.
Joules RTL Design Studio also enables users to leverage generative AI for RTL design exploration and big-data analytics with the company's expansive AI portfolio. Users can get fast, accurate physical estimates, unlocking up to 5X productivity and up to 25% quality-of-results (QoR) improvements in the RTL.
Who Needs It & Why?
For RTL designers, the sheer size and complexity of today’s SoC designs means they need earlier—and deeper—visibility into physical design. If the RTL code that’s handed off to implementation isn’t fully optimized, the RTL designer runs the risk of handing off code that will yield low-quality netlists. The physical implementation process can only hope to attain modest improvement to those netlists.
Thus, it behooves the front-end designer to avoid kneecapping implementation. Joules RTL Design Studio accomplishes just that by shedding light onto critical physical aspects of the RTL code: power, performance, area, and congestion (PPAC). Armed with that insight, the RTL designer can then resolve a large portion of physical implementation challenges posed by their formative code, and by doing so, reduce the number of iterations between RTL design and physical implementation.
Under the Hood
Joules RTL Design Studio brings a host of productivity-enhancing features and benefits. For one, it offers an intelligent RTL debugging assistant system, which is what delivers those critical early PPAC metrics as well as actionable debugging information throughout the design cycle—logical, physical, and production implementation. This enables exploration of “what-if” scenarios and potential resolutions to minimize iterations and improve design outcomes.
The tool is based on proven engines, as it shares the same trusted engines as Cadence’s Innovus Implementation System, Genus Synthesis Solution, and Joules RTL Power Solution. Thus, users may access all analysis and design exploration features from a single GUI for optimal QoR.
Joules RTL Design Studio also provides powerful AI integrations, such as integration with Cadence’s generative-AI solution, Cadence Cerebrus Intelligent Chip Explorer, to explore design space scenarios, such as floorplan optimization and frequency-vs.-voltage tradeoffs.
In addition, the Cadence Joint Enterprise Data and AI (JedAI) Platform allows for trend and insight analysis across different versions of the RTL or across previous project generations. There’s also integration with lint checkers, so that users can run such tools incrementally to rule out data and setup issues up-front, reducing errors and time to completion.
Finally, the tool’s unified cockpit provides RTL designers with an efficient, user-friendly experience, offering physical design feedback, localization and categorization of violations, bottleneck analysis, and cross-probing between RTL, schematic, and layout.
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For more information, visit the company's website.
