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How do you get the optimum system-on-chip (SoC) design? Becoming expert in all aspects of SoC design is impractical. There are too many features to address. Getting some help and building on the work of other experts in the field is the way to go.
The Synopsys Designware HPC Design Kit delivers more than 125 design cells and memories optimized for speed, space, and power. It can be applied to SoC designs that incorporate single-core or multicore CPUs, GPUs, and DSPs. It supports the latest TSMC 28-nm process today and is expected to extend this to other process nodes soon.
The new package can be applied to any design. It is different from the ARM's Processor Optimization Package (POP), which targets specific architectures like the ARM CPUs. POP-style solutions are great when dealing with the main CPU, but this latest kit works with any CPU, GPU or DSP core. It is probably unnecessary and possibly impossible to mix these approaches, but the new HPC kit will be ideal for custom designs.
The HPC kit includes a range of flip-flop designs (see the figure). Each optimizes a different set of criteria. It would be great to have one design that is the smallest, fastest, and most power efficient, but normally there are tradeoffs so the fastest is not the most power efficient.
Critical-path designs can benefit by using a flip-flop that optimizes the delay from input to output. This adds more time to the critical path. Likewise, a flip-flop that can extend the setup time also adds time to the critical path, resulting in the ability to incorporate more logic between the two different flip-flop implementations. Logically they are the same at both ends, but the timing details are different.
In some instances, speed or critical-path timing is less of an issue. In this case, space and power efficiency can be optimized. Register designs that allow clock logic to be shared help. Synopsys calls these register designs multi-bit flip-flops. Also, the range of cells is an advantage when mixing CPUs, GPUs, and DSPs in an SoC. CPUs may have a very high clock rate compared to the GPUs and DSPs in the mix. Using area optimized 2-port memory ensures lower area and power implementations of GPUs.
The selection of design cells still requires tradeoffs, but targeted designs permit optimization for particular sets of attributes. Proper selection improved performance by 10%, reduced power by 25%, and reduced area by 10% for Imagination Technology’s PowerVR Series 6 core.
The kit also helps reduce turnaround time. Part of this improvement is from using finely tuned cells to expedite design closure. Furthermore, Synopsys offers a FastOpt service. Synopsys designers can take as little as four weeks to help optimize an SoC design.
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