This video/article is part of the TechXchange: Chiplets - Electronic Design Automation Insights.
What you’ll learn:
- What are the benefits of using chiplets?
- Challenges that arise when implementing chiplets.
In the video above, Electronic Design’s Bill Wong talks with Syed Alam, the Global High Tech Industry Lead at Accenture, about the advent of chiplets and how they may help overcome the challenges with Moore’s Law. The article below goes into more detail about the technology.
For the past couple of decades, most semiconductor advances, capabilities, and innovations have happened on the front end. This technological progress has been accompanied by increasingly more complex designs and smaller geometries, currently culminating at the 3-nm process node. Lately, though, achieving Moore’s Law has become more challenging and costly, to the point where building a 5-nm chip is now more costly than building 10- and 7-nm chips combined.
As the benefits of scaling continue to decrease with each new node, chipmakers are turning back to a concept nearly a decade old: Rather than manufacture a chip on a single piece of silicon, they’re combining individual functional die, also known as “chiplets,” which might be the next frontier in achieving Moore’s Law and advanced manufacturing at scale.
Top Architectures Involved in Chiplet Design
As previously mentioned, manufacturing a chip on a single piece of silicon (commonly referred to as systems-on-chips or SoCs) has led to skyrocketing costs. One path to achieve the same level of performance at a fraction of the cost is by combining chipsets with different functions. There are three mainstream architecture designs for compiling chiplets:
- Fan-out: Fan-out utilizes dice and redistribution layers to combine different chiplets. Fan-out isn’t as fast or power efficient as other architecture systems, but it’s more easily testable and therefore has a faster time-to-market.
- 2.5D: 2.5D packaging methodology uses an interposer for stacked inter-chiplet communication, leading to a higher communication rate. It can be paired with stacked memory modules to create high-performance modules. However, the interposers that enable 2.5D architecture are expensive relative to the other methods.
- 3D: 3D is the same general idea as 2.5D with chip stacking, but it involves stacking logic on logic chiplets with through silicon vias (TSVs) to yield the highest-performance chip designs.
Why Major Companies are Betting on Chiplets
Companies such as AMD or Intel have designed their own chiplets and interconnects for some time, although mostly through proprietary components and design. Now, other semiconductor firms like NVIDIA are also exploring chiplets, driven by the diminishing power and performance benefits achieved by transitioning to new nodes and the growing complexity and costs of scaling.
This shift hasn’t gone unnoticed by countries looking to bolster domestic manufacturing either. The U.S. Chips and Science Act authorized $2.5 billion last year for an advanced-packaging R&D program, while China is offering tax breaks and incentives for similar investments.
Indeed, as requirements get increasingly complex, advanced packaging seems a cost-effective way to combine chips while reducing RC delays. Chiplets also make it easier to develop customizable, complex systems more quickly while enabling the sourcing of chips from multiple vendors, thus lowering the barrier of entry and reducing the risk of supply disruption.
Moreover, chiplets may help the industry better deal with persistent thermal issues seen in advanced architectures. This, in turn, will improve reliability relative to traditional SoCs.
Challenges Remain for Chiplets
As mentioned earlier, the concept of chiplets isn’t new, but adopting it for modern chips is much more complex than it was for the multichip modules of the past. This is one reason why foundries and integrated device manufacturers are building their own ecosystems.
However, it will be much more difficult to create a commercial chiplet marketplace in which chiplets from multiple vendors are developed according to the agreed standards so that they’re compatible with one another and truly plug-and-play. This effort requires collaboration across the industry and could take the better part of a decade until achieving an industry-wide breakthrough. Recently, large semiconductor players formed a consortium called Universal Chiplet Interconnect Express (UCIe) that may serve as a basis for a multi-vendor future state.
To realize the potential of chiplets as the next frontier in semiconductor innovation, sourcing, manufacturing, and packaging must happen in a standardized, repeatable, and scalable fashion.
Chiplets: Carving a Path Toward a Smarter World
At a time when manufacturing advanced nodes and achieving Moore’s Law is becoming increasingly complex and cost-prohibitive, chiplets appear as a viable way forward to obtain design flexibility, reduce development time and costs, and lower power consumption. But doing so will require a coordinated effort that involves reimagining semiconductor ecosystem needs to allow for industry-wide interoperability and integration.
Chiplets have all of the ingredients to enable the next advance in chip performance. Investments made by major industry players, government incentive programs (e.g., CHIPS Act, EU CHIPS Act, etc.), and ecosystem partnerships can all come together to make chiplets an approach that garners support across the industry. The implication is huge: Chiplets are bound to solve long-standing industry challenges such as increasing costs and supply disruptions, resulting in a world where devices are more intelligent than ever.
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