Micron Technology recently unveiled 176-layer, triple-level-cell (TLC), 3D NAND flash memory with a 30% smaller die size that employs a new replacement-gate (RG) NAND technology. The chips offer a 35% read/write latency improvement as well as a 33% increase in transfer rate, which is now 1600 Mtransfers/s.
The chips are actually built from a pair of 88-layer stacks. When making a 176-layer stack, the challenge is the difficulty in ensuring uniform construction up and down the stack. The latest chips follow on the heels of the 128-layer device from Micron, which also employed 3D NAND and 64-layer stacks.
The challenge that RG NAND addresses is the capacitance between cells (Fig. 1). The RG NAND architecture employs a single insulator structure that minimizes the capacitance between cells to almost zero. Each TLC stores three bits of data.
The change to RG NAND improves write endurance and power efficiency while the smaller size boosts overall capacity. Write speed is faster, too, at almost twice that of conventional NAND because the ramp time for programming is reduced by the lower capacitance levels. RG NAND also allows the voltage threshold saturation to be increased so that a cell can hold a larger charge.
With 3D RG NAND, a wider pillar can be built that’s more stable; therefore, more layers can be used in a stack (Fig. 2). The memory stack only contains storage elements as Micron utilizes a CMOS-under-the-array (CUA) approach. This puts the management logic on the bottom layer of the chip with memory layers built on top of it.
