As part of its annual Architecture Day, Intel unveiled what it called its largest architectural shift in a generation with a pair of new x86 microarchitectures, code-named Gracemont and Golden Cove.
The Santa Clara, California-based company revealed new details about the “Performance” and “Efficient” cores, both of which bring major leaps in speed and efficiency over their predecessors. It also revealed details about its latest generation of Core CPUs, called Alder Lake, which will bundle the cores in a hybrid architecture for desktops and laptops. Alder Lake will be available for desktops in late 2021.
The Context
Intel is trying to get its act together after falling behind on the development of its most advanced process technology. The Silicon Valley company has been losing ground to AMD, which has released chips based on its Zen 3 CPU architecture and TSMC's 7-nm node that can challenge Intel's. It is under pressure from Qualcomm, Nvidia, and other rivals trying to loosen the chip-making giant's grip on data centers and PCs.
At the start of the year, Intel hired Pat Gelsinger as chief executive officer with a mandate to rebuild the company's chip development process and regain ground being surrendered to a growing horde of rivals.
Modern processors are bundles of billions of transistors and interconnect arranged into logic gates on slices of silicon. But as semiconductor firms struggle to roll out smaller and smaller transistors, Intel is leaning harder on its CPU architecture to wring more performance out of its existing factories. It is also banking on its 3D advanced packaging to help close the gap in performance with TSMC and other foes.
Raja Koduri, senior vice president and general manager of accelerated computing and graphics at Intel, said: "These architectural breakthroughs set the stage for our next era of leadership products." He said that they highlight "how architecture will satisfy the crushing demand for more compute performance as workloads from the desktop to the data center become larger, more complex, and more diverse than ever."
The Cores
The new x86 cores are designed to play different roles in Alder Lake. Intel said the “Efficiency” core (also called “e-cores”) would bring improvements in performance and efficiency over Intel’s Skylake core and run multithreading. The “Performance” core (or “p-cores”), which can only process one thread at a time, will deliver a major boost in general-purpose computing power for both consumer and data center CPUs.
Unlike traditional Intel chips that combine several cores all based on the same design, Intel plans to meld the smaller, high-efficiency and the larger, high-performance cores in a "hybrid architecture" in Alder Lake. The layout resembles Arm’s big.LITTLE architecture used by Apple and Qualcomm to package clans of potent, power-hungry cores and smaller, simpler cores on a chip to boost battery life for smartphones.
While it is modeling Alder Lake on the types of power-sipping chips inside Apple's iPhone and other mobile phones, Intel is focusing more on maximizing performance for workloads with lots of threads.
"Performance" Core
Intel said the new performance core, previously code-named Golden Cove, is the most formidable CPU to come out of Intel—in a scalable architecture that spans from laptops to desktops to data centers. Golden Cove, the successor to Intel's 10-nm Sunny Cove microarchitecture, pushes the envelope in single-thread performance by uncovering more ways to carry out computations in parallel while reducing latency.
Golden Cove pumps out 19% more performance on a wide range of general-purpose workloads than Cypress Cove, a 14-nm variant of Sunny Cove used in Intel's 11th-generation Core processors.
The philosophy behind Golden Cove was a "wider, deeper, and smarter" microarchitecture. Intel said it reinforced the front end of the pipeline to handle and decode more instructions in a shorter span. It also rebuilt the branch prediction mechanism, a component inside the CPU that predicts the next operation in a program, to be more accurate. That means it makes incorrect predictions less often, leading to better performance.
Intel said it also bolstered the back end of the processor’s pipeline with deeper out-of-order buffers, a wider allocation window, and more execution ports. It enlarged the memory subsystem while reducing the latency of the L1 cache - the memory bank where the core stores its most vital instructions - and boosting the speed of the L2 cache, which can total up to 1.25 MB in PCs or up to 2 MB in server CPUs.
Intel also said it incorporated its new power management engine to better budget power depending on the work in progress, resulting in a higher average frequency for any program running on Golden Cove.
Intel said chips based on Golden Cove could take advantage of new instruction sets, such as Advanced Matrix Extensions (AMX), which represent the next generation of Intel's internal AI accelerator for training and inference. Intel said AMX, which complements its advanced vector extensions (AVX-512), includes dedicated hardware and a new instruction set architecture to carry out machine learning chores at a significantly faster pace.
Intel said AMX allows the performance core to perform eight times more INT8 operations per cycle than the Vector Neural Network Instructions (VNNI) technology used in Intel's previous generations of CPUs.
"Efficient" Core
Intel said the Efficient core, previously known as “Gracemont,” is the most efficient x86 microarchitecture in its lineup and offers far more performance than Intel's legacy Skylake CPU cores. Intel said Gracemont has high throughput to run through workloads with many threads and offload less strenuous tasks. Intel engineered Gracemont to fit in a minimal silicon area so that workloads can scale out with the core count.
Intel said it upgraded the underlying architecture to run workloads without wasting any unnecessary computing power while giving it the headroom to operate at higher frequencies. Intel improved its ability to predict the next instruction in a workload more accurately. It enlarged the L1 instruction cache to 64 kB to keep useful instructions close and prevent it from wasting power by traveling to other memory banks.
Gracemont features a deeper front end paired with a wider back end with more execution ports than its previous Atom-class microarchitecture, code-named Tremont. Intel also placed a clustered out-of-order decoder in the pipeline to decode more instructions every cycle while keeping power and latency in check. Also under the hood is a unique instruction length decoder that stashes pre-decode information in the L1.
For single-thread performance, the Efficient core is 40% faster at the same power as the Skylake core, the most widely used CPU microarchitecture in its lineup. But, conversely, it can consume 40% less power at the same performance level. Intel said four Efficient cores offer up to 80% more throughput at less power than 2x Skylake cores running four threads. Or they can deliver the same throughput for 80% less power.
Transistor density is another priority Intel is addressing with Gracemont. Intel can fit four Gracemont cores in the same footprint on a die as a single Skylake core, which it introduced half a decade ago.
