Intel Partners with Top EDA Vendors to Further Foundry Ambitions

Intel said it has partnered with the world's top electronic design automation (EDA) software firms as it moves to build a vibrant ecosystem of support and services around its new foundry services business.

The Santa Clara, California-based company has enlisted Ansys, Cadence, Siemens EDA, and Synopsys to become part of its "IFS Accelerator" program. Under the program, Intel said it will give them early access to its process and advanced packaging roadmaps, process design kits (PDKs), and a range of other resources.

The close collaboration will allow the companies to fine-tune their chip design software for Intel's latest process and packaging technologies so that Intel's foundry clients can best realize their performance, power, and area goals, while reducing their time-to-market.

Designing a modern chip is a complicated process that can take months or even years. It is impossible for even the most skilled engineers to design every single detail by hand. Intel and other chip vendors use EDA software that assists in planning, designing, verifying, implementing, and testing the chip before it is even made. That way, engineers can save themselves time and focus on more important aspects of a  design.

IDM 2.0

Intel has stumbled in recent years, falling behind competitors in designing the most advanced chips and manufacturing them, shaking its dominance of the industry for the first time in a long time. Intel CEO Pat Gelsinger is looking to lead Intel out of a prolonged period of turmoil and regain its technology leadership from TSMC. TSMC is world’s largest player in the foundry sector with over 500 customers, including Intel.

As part of his "IDM 2.0" strategy, Intel has pledged tens of billions of dollars to bolster production capacity, including at its sprawling new $20 billion manufacturing site in Ohio. It is also building a business to make chips for other firms, and even rivals, based on their blueprints. Intel has landed deals with Qualcomm and the U.S. Defense Department, and last year, it said it has had discussions with 100-plus potential clients.

But to make the process of designing a chip for its factories as easy as possible, Intel needs to become part of the same foundry ecosystem as TSMC and other players in the made-to-order chip business. That means making sure its process and packaging technologies are compatible with popular EDA tools. 

Cadence, Synopsys, and other software firms Intel is now working with have partnered with virtually every major foundry in the sector over the years. That way, when TSMC rolls out a new generation of process technology, they already have tools that can take into account new rules for placing and routing transistors and interconnects as well as laying out the floorplan of the final chip, among a host of other factors.

Said Joe Sawicki, executive vice president of IC-EDA within Siemens' software division: “Strong partnerships between foundries and industry-leading EDA tool providers are becoming increasingly essential in getting next-generation designs developed on time." 

These relationships are even more important as Intel introduces new transistor technologies such as its gate-all-around transistors called RibbonFETs and backside power-delivery system known as PowerVia.

IP Partnerships

Intel said on Monday that it has also partnered with a range of companies, including Arm and SiFive, to build out a broad library of intellectual property (IP) that is optimized for its latest technology nodes. 

"Foundry customers need access to design services, IP, and tools and flow to enable their next-generation products in different stages,” said Randhir Thakur, who leads Intel's foundry business and was previously responsible for Intel’s supply chain and manufacturing operations. He added that the new relationships would help the company to "deliver a seamless interface with Intel’s process and packaging technologies."

"Intel is wholeheartedly embracing the idea that innovation thrives in an open and collaborative environment," Thakur said.