Intel's Foundry Business Works with Arm, SiFive to Support IP
Intel said that it is partnering with Arm, SiFive, and many other major vendors of intellectual property (IP) blocks in chips, with the goal of building an ecosystem to support its new foundry services business.
The Santa Clara, California-based company announced it will work with AlphaWave, Analog Bits, Andes, Arm, Cadence, SiFive, Silicon Creations, Synopsys, and Vidatronic to assemble a broad range of building blocks that its customers can plug into modern chips. It will collaborate with them as part of a program called "IFS Accelerator" to make sure their IPs work with Intel’s process and packaging technologies.
Designing a system-on-chip (SoC) with integrated and reusable IP blocks has become the standard as chips get more complex. But every new process node requires a whole new suite of IP to be developed.
Intel said the IP portfolio it is building with Arm and others will include all of the key building blocks for a modern chip: standard cell libraries, embedded memories, general-purpose I/Os, analog, and interface IP.
Intel is trying to recover from years of disarray, when it fell behind rivals in designing the most advanced chips and building them, shaking its dominance for the first time in years. CEO Pat Gelsinger is trying to revive Intel's fortunes and transform it into an even more sprawling behemoth that builds chips for other companies (and even some rivals) based on their blueprints and using its process technologies.
As part of its IDM 2.0 strategy, Intel is investing tens of billions of dollars to boost production capacity, including a $20 billion manufacturing site in Ohio that will be made available to foundry clients.
Furthermore, the company is opening up its treasure trove of x86 CPU cores and other IP to customers in its foundry business. Intel said it would also support companies that come to it with their own in-house IP based on Arm or RISC-V. Customers will have access to the same advanced packaging technologies, too, including embedded multi-die interconnect bridge (EMIB) and other tools Intel uses in its chips.
Packaged Goods
Intel is also looking further into the future, as more chip vendors move from a system-on-chip (SoC) to a system-in-package (SiP) approach and lean more on 2.5D and 3D advanced packaging technologies.
The system-in-package approach gives companies a way to partition chips into modular slabs of silicon known as “chiplets” or “tiles.” Every tile is fine-tuned for a specific function, allowing companies to mix and match capabilities and process technologies, sometimes even using more than one ISA in the same chip. Reusing IP also reduces development cycles and cuts the time and cost of bringing a new chip to market.
Intel also announced plans to work with several cloud computing firms to build an open chiplet platform that will allow its customers to combine tiles with different functions from varying foundries and based on different process nodes.
Many cloud computing firms are trying to build custom server chips for their data centers. They are also looking to tack on their in-house accelerators, with the goal of speeding up workloads such as networking and machine learning. Integrating an accelerator tile in the same package as a server's CPU brings better performance and power efficiency than placing an accelerator card next to the CPU in a server, Intel said.
The open chiplet platform will leverage Intel’s advanced packaging tools as well as IP optimized for its latest process technologies, supported by integration and validation services to reduce time to market.
It is also open to working with other industry leaders to build an open die-to-die interconnect standard that allows chips from different foundries and on different nodes to communicate with each other in a package.
“Intel is an innovation powerhouse, but we know that not all good ideas originate from within our four walls,” said Randhir Thakur, president of Intel's foundry arm.
