This article is part of the Electronics History series: The Graphics Chip Chronicles.
Reality Simulation Systems (RSSI) was founded in 1993 at Rensselaer Polytechnic Institute’s Venture Creations, RPI’s incubator in Troy, New York, by Mike Lewis and Steve Morein. The goal was to develop a very high-performance, cost-effective 3D graphics processor for the interactive electronic entertainment market.
The company developed a tiling design called PixelSquirt. Morein was the lead designer of the company’s first chip and was inspired by Microsoft’s Talisman project and VideoLogic’s PowerVR.
In 1994, Lewis and Morein moved to San Jose to be closer to the action in Silicon Valley. Lewis attracted interest from angel investors and, in 1995, was able to raise additional capital to enhance the design further.
Lewis and Morein said the 3D PixelSquirt architecture offered several improvements over traditional methods of 3D rendering. The architecture, said Lewis, addressed the bandwidth and memory requirements to achieve visual realism for 3D at 1024 × 768 and higher resolutions, the standard for high-resolution established by IBM in 1987 with the 8514/A.
Enter S-MOS
In 1996, S-MOS Systems and RSSI announced a long-term development and marketing agreement to design 3D technology and products for personal computers. S-MOS worked with Steve Morein to develop the SPC1515 PIX.
Morein said at the time, “Even with the drop in memory prices it doesn’t pay to reinvent 2D. Instead, make it [the PIX] work with any card that supports DirectDraw surfaces.” When asked if the engineering team would take advantage of Tseng’s IMA port, Morein remarked they were investigating this method.
When asked about competitors, Sandeep Gupta of S-MOS said, “Rendition, maybe, but the real competition is a pair of skates for a Christmas present.”
RSSI avoided lookup-write backs to the CPU, and it instead used 250 kB of on-chip cache. It also developed special-purpose code that could take advantage of the Pentium’s dual pipeline, similar to a traditional image generator. Morein said the next version of the chip would tap AGP (Accelerated Graphics Port).
The SCP1515 performed point-sampled texel-address calculations for texture mapping and supported 32 × 32 to 1024 × 1024 resolution maps. Textures were stored in the host-system memory, and the chip managed 65,536 separate texture maps and up to 128 MB of addressable texture-map data. PIX also supported PCI burst transfers.
When asked about comparisons to the streaming processor concept of Talisman, Morein said, “We started with tile and rejected it. They do a nice job, but it’s better if you don’t have to use them. We do texture lookup after visibility. Render into texture maps, then software texture lookup.”
Morein said that it was able to sustain data-transfer rates greater than 100 MB/s over PCI, but it wouldn’t work with VGA chips that insert any “not-ready” commands. At full power, the chip ran at 66 Mpixels/s (Z-buffered, 640 × 480). At 800 × 600, the chip reached 45 Mpixels/s.
Under the terms of the agreement, S-MOS would provide the manufacturing through its affiliate, Seiko Epson in Japan, while also offering worldwide sales, marketing, and co-development resources. RSSI would provide key technology and design expertise in all phases of development. The partnership was a breakthrough and validation for RSSI.
Seiko was (and still is) a very well-respected precision technology company, and the Japanese are highly diligent in their partnerships. The last thing the 115-year-old company wanted was to be embarrassed or have its reputation damaged.
Tom Endicott, vice president of S-MOS marketing and sales, said, “We chose to work with RSSI because of their unique and innovative approach to three-dimensional design for personal computers and their specific knowledge of the computer games market. While others were approaching the problem of 3D graphics from a workstation point of view, RSSI approached the problem from the PC user’s point of view.”
The first chip of a planned three to come out of the agreement was the SPC1515 or PIX (PixelSquirt). S-MOS announced it was targeting video games and VRML 3D. Lewis said S-MOS would use existing 2D graphics subsystem buffer memory and main memory to reduce cost and improve performance. When S-MOS forecasted the bill-of-material (BOM), it said it would cost $60 for a 3D upgrade board with the PIX. That was an aggressive price for the market segment the company was targeting. But as it turned out, it was not realizable.
S-MOS introduced the concept for the graphics chip at the 1996 Computer Game Developers Conference. The firm was optimistic it would have a motherboard design win to announce soon. But it never made it into production.
RSSI: PixelSquirt
RSSI’s frame-buffer-less PixelSquirt debuted at the 1995 CGDC. At the conference, RSSI’s president David Bernstein said, “Our relationship with S-MOS has created an excellent working partnership to enable the complete development and introduction of our flexible 3D graphics technology. The simplicity of RSSI designs combined with S-MOS’s first-class manufacturing facilities will allow very quick product cycles, as demanded by the PC marketplace.”
RSSI developed a scalable image generator. High-performance visualization and simulation systems like flight simulators used image generators. For increased performance, it was possible to daisy-chain several PixelSquirts together.
The company built an add-in-board (AIB) with four PixelSquirts and a master controller. The AIB accepted a video stream from a VGA board via the feature connector and then shaded the polygons. It pulled in polygon edge information via the PCI bus. It rendered at 100,000 flat-shaded 400-pixel triangles/s, with a more than 3-Gpixel/s fill-rate.
The AIB could deliver 2,000 triangles per frame, independent of the frame rate. The AIB offered 24-bit color with a 1-bit alpha plane and a 24-bit Z-buffer. The chip supported resolutions up to 1024 × 768.
RSSI offered the four PixelSquirts, with a DAC and a master controller chip on an AIB they called LittleSquirt, with an estimated price of less than $500. Although the AIB was not appropriate for gamers’ budgets, the design showed off the company’s capabilities, and the price was cheaper than standard image generators. But, even with S-MOS’s support, military and commercial aircraft companies balked at working with such a small company. As has been proven too many times, big companies like to deal with big companies.
In mid-1997, the company began work on a new architecture, Aquila PX, and teased an announcement for March 1998.
Aquila PX offered high-performance 2D, 3D, and video and simultaneous NTSC/PAL television output. Lewis said the design would deliver 100 Mpixels/s. It had a floating-point setup engine, a 4K texture cache, a 230-MHz LUT-DAC, and a nonlinear three-line flicker filter for television output. Lewis said Aquila PX supported a 1024 × 768 × 16 resolution with a 1-MB texture buffer in a 4-MB configuration.
A follow-on chip, the VelaTX, was a 3D-only processor that Lewis claimed could reach 250 Mpixels/s, and it incorporated many advanced 3D features such as anisotropic texturing. VelaTX would work with any existing 2D graphics accelerator, claimed Lewis. The 3D cores from both devices were available for licensing.
In 1997, Morein left RSSI and moved to AMD. Aquila PX never made it out of the laboratory. But in 1998, the company announced its VelaTX.
Stellar is Born (1997)
In late 1997, RSSI was restructured and renamed Stellar Semiconductor. With assistance from Sky Capital, Stellar purchased RSSI's assets, which included a design for a new 3D chip code-named Aquila PX. Some executives left S-MOS Systems to help establish the company, including Sandeep Gupta. Gupta had been the senior product manager for graphics products at S-MOS and became Stellar’s CEO. Joseph C. Del Rio, VP of engineering and co-founder of Stellar, was the executive director of engineering at S-MOS. And Michael Lewis, the company’s CTO, was with RSSI before moving to Stellar.
The company launched at the 1998 Intellectual Property in Electronics Seminar (IP98) in Santa Clara, California. The company had more than 25 employees then and completed two rounds of venture financing. At the time, S-MOS was still pursuing its own course.
Due to pending patent applications, scant details were available at the time. Gupta said the design would achieve high performance, high resolution, and high-quality realism. Furthermore, the architecture (like Talisman and PowerVR) did not use a Z-buffer, and it featured a real-time data flow while using half the gates of alternative solutions. The architecture was developed in 1993 and was implemented in an AIB a year later.
Stellar planned to develop intellectual property (IP) for a 3D graphics engine. “We also plan to move into the fabless semiconductor business by creating, marketing, and selling graphics engines for the add-in card and motherboard desktop PC arena,” said Gupta. However, Gupta added that the Stellar graphics accelerator would target a niche market in the 3D space, one not well-served by other graphics companies.
Stellar had two licensees signed up for its 3D core but would not comment on who they were. Broadcom was most likely one of them.
The company planned to introduce a proprietary 3D graphics engine in the second quarter of 1998 as a synthesized HDL netlist, and it claimed to have two foundries qualified to build it.
The first 3D core was DirectX 5.0 compliant, and the company said it would use less than 250,000 gates and be synthesizable up to 100 MHz. Stellar claimed to have proven the core twice in silicon with software drivers using Direct3D and OpenGL. Gupta said it would take Stellar less than a week to hook the existing 3D core design into a company’s device. “Because the architecture is pipelined, a company can balance the performance loading and host interface effectively,” he added.
The 3D IP core and the graphics chips used RSSI’s original PixelSquirt architecture based on a parallel processor and a multiple pipelined design. PixelSquirt’s tiling engine eliminated the need for Z-buffering because it removed hidden surfaces before filtering, texture mapping, and atmospheric conditioning.
Stellar said a key advantage of its core was the ability to interface easily to existing host interface and memory controller blocks. In those cases, the host IF block was only required to provide a bus master read connection to the host CPU, and the memory controller only needed to provide a read/write interface to the memory for texture map storage. The company said the 3D core was small and highly scalable, and it offered a range of price and performance options to licensees. Stellar had five patents in prosecution at the time.
VelaTX (1998)
Stellar described VelaTX as the first of a family of 3D rendering engines based on the PixelSquirt architecture. The company claimed it would deliver 200-Mpixel/s rendering without Z-buffering. Z-buffer elimination, said Stellar, reduces the requirement for fast memory. Previously, PixelSquirt had been offered as a synthesizable core.
Instead of rendering one polygon at a time, the PixelSquirt rendered a pixel at a time in raster order, starting with 24-bit floating-point hidden-surface removal. The remaining operations act only on data output to the screen.
The chip had 2.5 MB of DRAM integrated with the renderer via a 512-bit bus to speed up texture mapping. Further texture storage used external SDRAM of up to 8 MB. Stellar said VelaTX would support numerous Open GL and DirectX 6 features in hardware, including perspective correction, specular highlighting, alpha-blend and texture-blend modes, multiple fog modes, and texture compression.
The design had an AGP-to-PCI bridge, P-Pipe, VIP/VMI ports, and a memory-expansion bus, allowing the chip to form a hub for multimedia expansion AIBs. The VelaTX was packaged in a 388-pin BGA and priced at $35 apiece in quantities of 10,000. Stellar said it would be available in the fourth quarter of 1998 or the first quarter of 1999.
Stellar and Sican (1999)
At the 1999 Intellectual Property in Electronics Seminar (ip99), Stellar and Sican GmbH (Hannover, Germany) announced a marketing and sales agreement. Sican agreed to market and sell Stellar’s IP cores alongside Sican’s existing library of core products. Sican would also offer design services to the customer base of Stellar.
According to Valentin von Tils, vice president of design for Sican, the IP core offerings from both companies would complement each other. Sican was offering audio and video decoding, broadband media access, and bus interface cores. Adding graphics to the mix gave Sican a bigger footprint in the multimedia, communications, and networking applications segments.
von Tils added, “Our combined strength will greatly enhance Sican’s ability to provide a robust set of cores for customers who are designing system-on-a-chip multimedia solutions in Europe.” The deal looked like a great fit, but it would be short-lived.
Broadcom Buys Stellar (2000)
After several months of negotiations, Broadcom announced it would acquire Stellar Semiconductor to help the maker of high-speed communications chips move into set-top-box (STB) and handheld internet appliance markets. “This acquisition provides Broadcom with an important piece of technology required to deliver high-end 3D games to digital set-top boxes,” said Broadcom CEO Henry Nicholas.
“After working with Broadcom for nearly a year, we’re excited about combining forces to address the burgeoning consumer digital entertainment market,” said Gupta.
Broadcom said it would account for the acquisition as a pooling of interest. A one-time charge would be taken in the first quarter to cover the expense related to the transaction.
Broadcom attempted to use the Stellar technology in an STB chip, but it struggled to find many OEMs willing to pay the price for the performance boost. In addition, cable companies did not have the content—or the bandwidth—to make good use of the Stellar technology back then. Lewis left Broadcom a few years later and, in 2015, started Mycroft AI, an open-source equivalent to Amazon Echo and Google Home.
Read more articles in the Electronics History series: The Graphics Chip Chronicles.
