Last year, SiFive went fishing for engineers to test out chips based on the RISC-V computer architecture. It released an embedded core called Rocket that could be downloaded and modified for free. But now the company is casting out richer bait.
Last week, SiFive started selling two cores under the brand Coreplex for applications like wearables and servers. The company is trying to make it easier to test drive the RISC-V architecture since not many engineers seem to be dissatisfied with rival technology from ARM or MIPS.
Licensing the cores takes little more than signing an online contract and making a one-time payment, which costs less than a million dollars. SiFive is making the register transfer level – more commonly known as the RTL – available immediately, so that engineers can simulate chips.
The announcement is a mile marker for the business, which launched in 2016. SiFive’s founders invented the RISC-V architecture, which provides starting instructions for making microprocessors. But unlike other instruction sets controlled by Intel and ARM, it is completely free and open.
SiFive works with customers on custom RISC-V chips, a practice that promises to reduce the millions of dollars and years of development required to make chips for markets like the Internet of Things. Its business model is similar to how Red Hat Software started selling its expertise with the free Linux operating system.
“Since the company was founded, we have actually had lots of requests from customers,” said Jack Kang, SiFive’s vice president of product and business development, in an interview. “They said, it’s nice to have open-source cores, but we want a commercial license that is well-supported.”
The Coreplex family includes the E31 core, a 32-bit processor that can replace the ARM Cortex M3 inside sensors and wearables. The other is the E51, a 64-bit embedded processor designed to serve as a controller in large chips or SoCs.
SiFive is trying to make it as easy as possible for engineers to experiment with its chips, since its biggest obstacle is building a developer community. It will not change royalty fees on Coreplex products, which means that all customers pay is $275,000 for the E31 and $595,000 for the E51.
Its sales strategy aims to eliminate the usual snags associated with licensing cores. Engineers will not have to contact a salesperson or sign a non-disclosure agreement to view datasheets. If companies want to purchase the cores, they have to sign a seven-page contract. There is no negotiation.
“In royalty-based models, companies have to know exactly what you are making and how many there will be,” Kang said. “But you can buy enterprise software online directly without talking to anyone. So we asked: why not bring that to hardware?”
Many companies are already looking into the RISC-V architecture. The RISC-V Foundation, which maintains the instruction set, includes members like Google, Microsoft, and Oracle, as well as IBM. Large semiconductor companies have also started using RISC-V.
After evaluating ARM, MIPS, and other embedded architectures, Nvidia recently started using RISC-V in the controllers for its graphics chips. Microsemi, one of SiFive's first customers, is already using Coreplex technology in its Igloo and other FPGA chips.
SiFive, whose founders – Krste Asanovic, Yunsup Lee and Andrew Waterman – invented the RISC-V specification, announced Monday that it had raised $8.5 million from Spark Capital and other investors. The start-up also said Monday that it had sold over a thousand of the Freedom development boards it released last year.
“It’s still the early days for RISC-V, so companies initially decided to try it without actually understanding what ‘free and open’ means," said Kang. "The biggest surprise is that it isn’t exactly what they were initially looking for.”
“But I think the sign of momentum is that companies say that they want more from us," said Kang. "We’ve really been surprised by how quickly RISC-V has grown.”
