Marvell Pushes to Get on Priority Line for TSMC's 3-nm Process
Marvell said it hopes to get an early jump on upgrading its server processors to TSMC's 3-nm process.
While the consumer electronics industry—and specifically Apple—has long pushed to the front of the line for new process technologies, Marvell has been working with TSMC to get its server-class chips into the priority line. The Santa Clara, Calif.-based company said it plans to start building more of its products out of chiplets (or tiles), using TSMC’s 5-nm node and its 2.5D chip-on-wafer-on-substrate (CoWoS) packaging technology.
Sandeep Bharathi, executive vice president of central system-on-chip engineering at Marvell, said it is poised to be the "lead vendor" to supply 3-nm chips for cloud data centers and 5G gear.
TSMC plans to ramp production of smartphone chips and other devices on 3-nm in next year's second half.
But upgrading to the 3-nm node is not only about improving its off-the-shelf server chips. Last year, Marvell opened a custom silicon business that works with cloud players, telecom giants, others to build chips that combine its in-house and customer IP. Marvell said that it is designing IP for TSMC’s 3-nm node, giving its customers the ability to roll out special-purpose chips that meet their unique cost, speed, and power needs.
Marvell also plans to roll out a pair of advanced die-to-die interfaces for 2.5D and 3D chip designs. The first is a flexible extra short reach (XSR) interface for connecting die on a package substrate, ideal for co-packaged optics for cloud data centers and other uses. It is also developing an ultra-low-power and reduced latency parallel die-to-die interface with high-bandwidth density. Designed to meet Open Compute Project (OCP) standards, these interfaces will allow Marvell to link together separate die on a silicon interposer.
Marvell is trying to transform itself into one of the more formidable players in the market for server chips used in the bowels of data centers and 5G infrastructure. The company is wrestling to win a larger share of the chip budgets at cloud computing giants such as Amazon AWS and Google, among others. Microsoft, for instance, had $24.2 billion in capital spending last year. A large portion of that was spent on its data centers.
Marvell expanded its footprint in the networking market with its $10 billion deal for Inphi, which sells chips for silicon photonics hardware. Last month, it also completed its purchase of switch chip startup Innovium for $1.1 billion.
It is unclear when Marvell plans to start shipping data center chips based on TSMC’s 3-nm technology node. It could be several months at least (and possibly more than a year) after the foundry starts mass production.
Marvell said that it has already started sampling its first 5-nm Octeon 10 DPU to potential customers.
A data processing unit, or DPU, is a type of networking processor that can be used in data centers to offload software-defined networking, storage, security, and any other infrastructure chores that can drag on the CPU in a server. By offloading these workloads to special hardware, the Octeon 10 saves CPU resources for other general-purpose software. Server manufacturers tend to add DPUs to networking cards called SmartNICs.
Marvell said the Octeon 10 is three times faster and consumes up to 50% less power than its predecessor, the Octeon TX2. The chip integrates artificial intelligence, packet processing, and cryptography engines, and it supports DDR5 DRAM, PCIe Gen 5 interconnects, and up to 400 Gbps Ethernet. The chip incorporates up to 24 CPU cores based on Arm’s Neoverse N1, introduced earlier in the year. The cores are clocked at up to 2.5 GHz.
The company said the Octeon 10 DPU is the first 5-nm server-class processor for use in cloud data centers.
Marvell rolled out its latest line of 50G Ethernet networking switches for 5G hardware: the Prestera DX 7300 series. The chips are based on the 5-nm node, giving them the same 50% efficiency gains as the Octeon 10.
The 5-nm Prestera switches also work with the Open RAN standard for 5G open radio access network gear.
