Intel is upgrading its flagship Xeon server CPUs to run wireless networks and networking gear in data centers more efficiently, as it moves to take on AMD, Qualcomm, and other rivals in the race for dominance in 5G.
The Santa Clara, California-based company said it plans to augment its next-generation Xeon Scalable CPUs called Sapphire Rapids with “signal processing instruction enhancements” specifically for 5G. Intel said the new instructions will help telcos upgrade a portion of their infrastructure called the radio access network (RAN). That includes key parts of the base stations they use to connect devices to their networks.
The Sapphire Rapids CPUs, which Intel will also sell to cloud-computing giants such as Alphabet’s Google, Amazon's AWS, Microsoft, and others, will be based on its most advanced Intel 7 manufacturing node, which taps its 10-nm technology. The chips feature the Golden Cove cores at the heart of Intel’s latest laptop processors.
Telecom firms are buying cellular base stations by the thousands to hook up to their 5G infrastructure in the U.S., China, Europe, and other regions around the world. The base stations are largely sold by telecom equipment giants Ericsson, Huawei Technologies, Nokia, and Samsung Electronics as all-in-one bundles, each with proprietary sets of hardware, software, and silicon that lock in wireless carriers that buy them.
But as part of the 5G rollout, telecom firms are moving to a new disaggregated RAN technology called vRAN, which leverages general-purpose CPUs and off-the-shelf gear from Intel and many other hardware vendors.
Disaggregated RAN
A base station in a disaggregated RAN uses a radio unit (RU) that houses the RF transceiver and other ICs to convert and amplify RF signals. The RU is generally located close to, or integrated directly in, the antennas. One of the other key components of a base station is the distributed unit (DU), which houses the baseband processor that runs the L1—or PHY—functions of the RAN protocol stack (or shares the load with the radio unit).
The DU is usually located close to and sometimes at the base of the pole to which the RU is attached. It is responsible for running baseband and signal-processing workloads, such as beamforming and channel coding. The central unit (CU) sits at the core of the network, where server CPUs run the management and control functions. These “functional splits” allow for flexible partitioning of workloads to various parts of a network.
Intel is targeting the computational parts of the RAN, from the network core to the bowels of base stations. It has amassed a 40% share of the global market for base station silicon with its “Snow Ridge” SoCs, which it sells to telecom giants such as Ericsson, Nokia, and others to run the DU in a disaggregated RAN, and FPGAs for the radio. Intel’s Xeon CPUs are widely used in CUs and carriers’ data centers.
Intel said the new instructions in the Ice Lake CPUs can handle the heavy computations for massive MIMO, a technology that allows for many more antennas to be attached to a base station. That boosts the base station’s power efficiency as well as the capacity of a wireless carrier’s 5G network. According to Intel, its latest Xeon CPUs can more than double the capacity that telcos can get out of 5G infrastructure.
Many telecom firms are also in favor of a new standard called Open RAN, which could loosen Ericsson, Huawei, and Nokia’s tight grip on the market. The standard promises to give carriers the flexibility to mix and match parts from different suppliers in the same base station, allowing them to roll out new features faster and at a reduced cost. The Open RAN standard would also rely on general-purpose processors, including those from Intel.
Intel also plans to expand its Sapphire Rapids CPU family in the future with new chips that feature “integrated acceleration” for vRAN workloads.
Inside The Xeon “D”
Intel introduced new Xeon “D” variants of its current Ice Lake CPU family, too. They are designed for data centers, base stations, and embedded systems in industries such as aerospace, defense, and industrial.
The first processor in the family, the Xeon D-1700, incorporates four to 10 CPU cores clocked at up to 3.5 GHz and up to 15 MB of cache memory. The Xeon D-2700 offers four to 20 cores and up to 30 MB of cache.
As a part of Intel’s previous-generation Ice Lake family, the Xeon SoCs support its latest instruction set improvements, including AVX-512 for running AI jobs inside the CPU itself, and cryptographic accelerators. The chips also have hardware security features such as total memory encryption and secure enclaves in the CPU—a feature Intel calls Software Guard Extensions (SGX)—to better protect data at the network edge.
According to Intel, the Xeon SoCs bring more compute density and throughput for non-server networking, storage, and security hardware in data centers, such as routers and switches, as well as wireless base stations and edge servers.
Intel said the Xeon SoCs offer 70% more performance than its previous generation for workloads used by telcos to manage their 5G infrastructure and up to 50% more for software-defined networks in data centers.
The company is bolstering its portfolio of 5G chips at a time when rivals are also increasing their focus on this market. AMD has completed its $49 billion deal to buy rival Xilinx, which sells FPGAs and SoCs that can be plugged into new 5G base stations. Smartphone chip giant Qualcomm and Marvell have rolled out accelerator cards that slot into the DU of a base station to offload beamforming and other chores from the CPU.
Networking Boost
Intel is also bringing a wide range of networking and I/O features into the fold with the new Xeon “D” SoCs.
The chips feature up to four DDR4 memory controllers that clock at up to 3.2 GHz and connect to 128 GB each, for a total of up to 1 TB. The chips include up to 32 lanes of high-speed PCIe Gen 4 and up to 24 lanes of legacy connectivity, including PCIe Gen 3, SATA, and USB 3.
The chips have up to eight Ethernet ports that supply up to 100 GB/s of throughput, with support for time-sensitive networking (TSN) and time-coordinated computing (TCC) to run real-time, robust networking on factory floors and other systems plagued by latency. These features improve time management for systems running real-time hypervisors, allowing them to carry out real-time workloads faster and more predictably.
The Xeon processors use high-density 45- by 45-mm or 52.5- by 45-mm ball-grid array (BGA) packages that can be mounted directly on a circuit board for ruggedness. They can also tolerate the harsh operating temperatures that a base station or other hardware at the edge is subject to out in the field.
Intel said the new Xeon SoC series will include 36 SKUs, with power envelopes ranging from 25 to 129 W. The chips will be used in servers from over 70 companies, including Cisco Systems and Juniper Networks.
