This article is part of the TechXchange: RISC-V: The Instruction-Set Alternative.
SiFive, a startup developing IP based on the RISC-V architecture, said NASA has selected it to supply the core CPU for the agency's next high-performance spaceflight processor, a big win for the emerging instruction set.
While SiFive will supply RISC-V CPU cores for the program, the space agency inked U.S.-based Microchip Technology to a $50 million contract to create the full high-performance spaceflight computer (HPSC). The chip is being designed for high-profile missions, including spacecraft for planetary exploration and future manned missions to the Moon and Mars. Microchip said that it will take three years to finish the work.
For NASA, the chips are intended to replace the PowerPC-based space processor that has been used in spacecraft ranging from the Curiosity and Perseverance rovers to the new James Webb Space Telescope.
At the heart of the processor will be an eight-core SiFive X280 RISC-V vector-optimized CPU, plus four general-purpose RISC-V CPU cores, giving it a 100-fold improvement in performance versus its predecessor.
The huge generational leap in performance will help usher in new possibilities for everything from spaceflight and guidance systems to autonomous rovers, vision processing, and communications, said SiFive.
Low Risk with RISC-V
While RISC-V is an open instruction set architecture (ISA), SiFive is building a business out of designing RISC-V CPU cores and offering them to other firms, which combine them with other IP in systems-on-chip (SoCs).
RISC-V is an open standard that's supported by a number of companies around the world. It stands in contrast to closed, proprietary architectures like Arm and Intel’s x86, subject to the whims of a single company, said Jack Kang, SVP of business development at SiFive.
Bonus points: Companies and countries are not getting locked into a single company for their entire product roadmap and product lifecycle, leaning on the likes of Arm and Intel for further research and development.
While RISC-V technology is becoming more widespread, it’s still the new architecture on the block. But that's partly why SiFive feels it’s the perfect fit for a platform that will remain in use at NASA for decades.
As Kang sees it, the RISC-V architecture is a safe pick for NASA. Even though the ecosystem around RISC-V is still in its early stages of growth, it's expanding rapidly.
Since NASA plans to use the space-grade processor for decades, “it is critical to pick an architecture that will have long-term support and growth,” he pointed out. “Which architecture will have the most engineers, programmers, and an ecosystem going for it 5, 10, 15 years from now? The previous space computer was based on proprietary PowerPC, developed 20 years ago—and look where that architecture is now.”
RISC-V, a reduced instruction set computer (RISC) architecture similar to Arm, is also gaining a foothold in U.S. universities, giving the nation a growing talent base that will know how to use it, said Kang.
“When you look at things from that perspective, the choice of the RISC-V ISA becomes [the] obvious winner.”
The open nature of RISC-V means everyone from semiconductor industry leaders to researchers have the freedom to contribute to it. Kang said, “The openness of RISC-V also brings with it a very large ecosystem of software developers, open-source communities, [and] commercial vendors. They all have a chance now to write software that will be used in these programs. Now, your code, if it’s the best, will be used in space.”
Space-Grade Instructions
RISC-V—frequently compared to Linux in the software world—has firmly established itself as one of the three major ISAs. The architecture has landed hundreds of millions of dollars in investment in recent years, in large part due to its open-source and free-to-use nature. The power of RISC-V is that you can add industry-standard and third-party extensions to augment CPU cores, without all of the constraints of Arm and x86.
The X280 is built on the 64-bit RISC-V instruction set. SiFive adapted the RISC-V CPU cores by adding vector extensions to give them a boost for digital-signal-processing (DSP) and artificial-intelligence (AI) chores.
For space-related workloads, SiFive said the X280 delivers several orders of magnitude more performance compared with rival CPU cores.
As part of the $50 million deal, Microchip will be the one arranging the RISC-V CPU cores into a space-grade SoC and surrounding them with the memory, networking, and connectivity required by NASA.
On top of its speed improvements, the space-faring processor will offer better power efficiency thanks to its ability to shut down various sections of the SoC when not in use.
The HPSC is also being designed to handle the hazards of spaceflight. The chips in satellites and other space-bound systems must withstand harsh vibrations and shocks that can cause damage when they are launched.
Moreover, electronics face major thermal-management challenges in orbit and further out in space. They must be protected against wide temperature fluctuations that influence how long they can survive in space.
Radiation hardening is usually required by space-bound chips to preserve their long-term reliability and performance. Damage due to radiation can lead to the catastrophic failure of processors operating in space.
Under these conditions, off-the-shelf processors would not last long before suffering a serious malfunction. As a result, a focus on fault tolerance, radiation hardening, and high reliability is another priority for Microchip.
Microchip has been supplying space-grade chips for years, ranging from radiation-hardened MCUs and FPGAs to memory and networking chips for satellites.
The Ecosystem Grows
This is the latest development in a major year for SiFive. Early this year, $175 million was raised in its latest funding round. Plans are to use the funds in part to speed development of its most advanced RISC-V CPUs.
The startup also partnered with Intel to optimize its leading RISC-V processor IP for the company’s process technology. The move was part of a $1 billion program funded by Intel to boost its foundry business.
NASA’s move also marks a milestone for the RISC-V ecosystem at large. The HPSC is being designed for use in virtually all future NASA missions, ranging from planetary exploration to lunar and Mars surface missions.
“Every new market segment brings with it more software ecosystem goodness, which is then further shared across all the other RISC-V ecosystems,” said Kang. NASA opting to use RISC-V CPU cores in its spaceflight processor further validates RISC-V as a viable alternative to rivals Arm and x86, he added. It also highlights the performance and power-efficiency improvements that companies such as SiFive are bringing to the table.
Microchip has signaled that it plans to offer the new platform to other customers outside of NASA.
Check out more coverage on the RISC-V instruction set architecture here.
