The clamor for multiple functionalities in next-generation wireless telecom and consumer electronic markets has designers scrambling to adopt a core-based design methodology. However, the lack of industry-wide standards for many aspects of core-based design, especially in test, poses a big challenge for designers who must integrate cores from multiple sources without any standard interface. The need for a set of standards becomes critical, especially when these emerging design methodologies are driven by core reuse.
The main driving force behind developing this architecture is the need for a test-interoperability standard for cores to ensure test reuse, and to enable plug-and-play at the chip level. Three key solutions to this problem formed the basis of our work: an architecture that combines cores with IEEE Standard 1149.1 \[IEEE 93\] taps on them; using a structured test bus framework that provides access to embedded cores; and a test-rail method to gain access to the cores.
Though these three approaches are very different, they have one common theme: test access for individual Virtual Components (VCs) with respect to stimulus pattern sources and output pattern sinks on an SoC. A VC is embedded in a silicon chip and is surrounded by other application circuitry. Sources and sinks for patterns could be primary inputs and outputs of the SoC, or they could be internal to the SoC in the case of an SoC with built-in self-test (BIST). SoC VC providers develop the test patterns that come with the VC for reuse, which requires that a test access specification, such as the VSI Test Access Architecture, be followed.
Given the importance of test access for testing SoCs, it was decided early on that the standard focus entirely on providing a standard interface to all cores. How the access mechanism is used is left to the SoC designer because different designs will have different needs, requirements, and limitations.
The VSIA Test Access Architecture Standard requires direct access to inputs and outputs of each VC. This is achieved with the wrapper register, which breaks the functional path of the inputs and outputs. In addition to the wrapper register, the standard requires a Test Control Block (TCB) and Bypass Register. Test application on a VC involves two basic steps. In the first step, the TCB is loaded with values (or instructions) appropriate for a test, such as external or internal. Depending on the values in the TCB, the wrappers may be configured to test the VC or the logic outside the VC, depending on the instruction. The Bypass register helps speed up data access to each of the VCs while bypassing the rest of the VCs in the design.
The standard was developed to provide a common test interface for IPs for integration at the SoC level. The immediate goal of the Test Design Working Group (DWG) is to raise awareness and encourage adoption of the standard. As part of this effort, the committee is exploring the possibility of implementing this standard on a pilot project by one of the member companies and using the project as a vehicle to validate the standard. The goal is to demonstrate a simple and robust approach that enables IP (VC) test reuse. By adopting the standard, the IPs can be delivered with a standards-based test interface used to deliver the presupplied IP test patterns from the SoC level. Thus, valuable time is saved in the design cycle by reusing test created at the IP level.
