Samsung Electronics, trying to boost its contract chip manufacturing business, recently announced plans to make chips based on 7-nanometer technology by the end of 2018. The company said that it would use a new photolithography process to tattoo transistors onto these chips, which process information more quickly using less power in less space.
The new production process could be the first to use extreme ultraviolet (EUV) lithography, giving Samsung more ammunition in the fight against market leader TSMC in the made-to-order chip business. And Samsung said that it would use EUV technology from the start to the end of the manufacturing process, rather than using it for only part of the process, something rivals are considering.
The company, which only last year split its semiconductor foundry into a separate business unit, gave the update at the recent Samsung Foundry Forum in Santa Clara, California. Samsung said that its 7nm Low Power Plus (7LPP) process would be ready for production in the second half of 2018, with mass production for customers expected to start by the first half of 2019.
Every chip today is manufactured by shooting intense beams of light onto silicon wafers, etching patterns where the light touches down. With existing technology, known as deep ultraviolet (DUV), the smallest transistors can only be etched onto silicon substrates by repeating the process over and over again—an extremely long, costly and complex process more likely to introduce manufacturing defects.
But many manufacturers are swapping out that technology as the cost and complexity of chips continue to grow. Using shorter wavelengths of extreme ultraviolet light, companies can reduce the number of patterning steps in the process, potentially lowering costs and improving yields. GlobalFoundries and TSMC have announced plans to introduce EUV commercially at the 7nm node in 2019.
But companies are still working on several supporting technologies around EUV. Samsung is reportedly moving ahead with EUV without pellicles to protect its photomasks—silkscreen-like devices that light shines through to transfer circuit patterns onto silicon—from contamination. The company is also reportedly building its own mask inspection tools, which like pellicles are not yet commercially available.
“Over the past year, we have focused on strengthening our EUV process portfolio,” said Charlie Bae, executive vice president of sales and marketing for Samsung’s foundry business unit, in a statement. “It is imperative for us to accomplish the first-time silicon success for our customers’ next-generation chip designs.”
Intel intends to switch over to the new photolithography tools with the 7nm node. But the company’s timeline is unclear. Intel has been struggling to complete its 10nm technology, which the company claims will let it squeeze more transistors onto chips than rival 7nm processes. Last month, Intel acknowledged persistent yield issues with its 10nm process, which would cause production to slip from the second half of 2018, into 2019.
Intel’s struggles expose the cracks in Moore’s Law, an observation made by Intel founder Gordon Moore that the number of transistors that can be etched onto a chip doubles roughly every two years, and which the industry has followed religiously for decades. But that faith in Moore's Law has flagged as new generations of chips get further and further apart. The slowing of Moore’s Law also came through last year when Intel fell behind Samsung as the world’s largest maker of chips by revenue.
The change coincided with the shuttering of the International Technology Roadmap for Semiconductors, an international effort to help keep the entire semiconductor industry on the same page of Moore’s Law. In recent years, Samsung has charted its own path, with plans to release single-digit nodes one after the other from 7nm to 3nm, which Samsung wants to put into production by 2021.
Currently, node names are pretty much arbitrary and don’t represent the actual width of the transistors, or any other feature, inside chips. But some analysts still say Samsung may be biting off more than it can chew after 7 nanometers. The company said that it wants to produce chips based on 5nm technology, which will consume less power and have more tightly packed transistors, in 2019. Samsung said that it would manufacture 4nm technology with smaller cell size and better performance in 2020.
Everything changes at the 3nm node. Samsung said that it would manufacture these chips using gate-all-around transistors. These structures differ from FinFETs, which are inside almost all chips manufactured since the 22nm production process was introduced, and which have vertical fins jutting out from the substrate. Gate-all-around transistors have horizontal fins, which act as silicon nanowires or nanosheets.
Last year, Samsung announced plans to use gate-all-around transistors in the 4-nanometer node. But the company claims to have gotten around the physical scaling and performance limitations of the FinFET architecture for another node. Samsung said that its gate-all-around transistors would be based on nanosheets to enhance gate control and significantly boost performance.
