Today, chips can be manufactured with a wide range of semiconductor IP, ranging from central processing (CPUs) and graphics processing units (GPUs) to power management and other analog devices, arranged on a single slab of silicon like articles on the front page of a newspaper. Not only are SoCs taking longer and longer to design, adding to overall engineering costs, but the manufacturing costs are also mounting.
Testing that the hardware and software are functioning correctly is also growing more expensive. Trying to change that is UltraSoC, which has announced a new debugging tool that can evaluate complete SoCs rather than just individual cores. UltraSoC said that the new UltraDevelop tool can trim development costs, save time and even enhance software running on multicore, multithreaded chips using a number of different architectures.
UltraDevelop is designed to be used with UltraSoC IP cores embedded inside the chip to detect malfunctions and other anomalies. The Eclipse-based tool gives customers insight into how hardware components are interacting with firmware and software after the chip is manufactured. That contrasts with traditional electronic design automation tools, which are typically used before the silicon comes out of the factory.
Last year, the company raised $6.4 million in venture capital to hire more employees and enhance its core development tools, which have won over customers including Microchip Technology, HiSilicon, Intel and Pingtouge Semiconductor. The company, led by chief executive officer Rupert Baine and founded in 2005, has also developed debugging tools that support the new open-source RISC-V architecture.
Designing chips today means mixing and matching semiconductor cores from different vendors, often based on different CPU architectures like ARM, RISC-V and MIPS. To support computer graphics or machine learning, accelerators such as Imagination’s GPUs or Cadence’s DSPs are also embedded in the system. But the shift to smaller technology nodes has introduced new power and thermal limitations that raise manufacturing costs.
Other factors are exacerbating development costs. These components are swapping information more frequently to support new applications in data centers, smartphones, factories and cars. To handle machine learning tasks, the central processor needs to move massive amounts of data into the memory controller and accelerator, both of which will interact with other plots of circuitry over the network—the NOC—holding the chip together.
“Today's SoCs, with heterogeneous multicore now being common, face the challenge of systemic complexity—and that is driving the ever-increasing cost of SoC design,” Semico Research analyst Rich Wawrzyniak explained in a statement. He added: “Tools that can view the SoC as a whole, not just in vendor silos, can have significant impact on engineering productivity and, in turn, on time-to-market and engineering cost.”
Instead of using separate tools for every architecture inside the chip, UltraSoC says UltraDevelop allows customers to view the whole system. The tool can simultaneously handle more than 20 processor architectures, including ARM, MIPS and RISC-V, among others. UltraSoC said that the new product will be available to early customers in the first quarter of next year. General availability will follow close behind, the company said.
The tool uses artificial intelligence to more accurately detect anomalies, locate hotspots and uncover the root cause of faults. These new capabilities could be used to test automotive chips for functional safety or detect security vulnerabilities, such as an unauthorized process trying to access protected memory. UltraSoC also said that they could be used to identify inefficiencies or other bugs in the software running on top of the chip.
“While simulation and emulation have progressed”—with new electronic design automation software—“integration and validation have not,” Semico’s Wawrzyniak pointed out. “Development teams are crying out for technologies that help them manage that complexity, and that means giving them the capability to view their designs in real-time, interactively, and at just the level of detail they require.”
