Commercial-off-the-shelf (COTS) software-defined radio (SDR) products have been traditionally used for military radar and communication applications due to their performance and design flexibility. The latest SDR products offer solutions with integrated I/O, Arm processors, and large FPGAs that include intellectual property (IP) for accessing, routing, and processing digital data. Combining these attributes with superior signal integrity, phase-coherent sampling, and multichannel transceivers, a COTS SDR system becomes an ideal choice for a 5G development platform.
The Latest COTS SDR Technology
Over the past 10 years, FPGA manufacturers like Xilinx have been improving technology by reducing the silicon fabrication structure size and, as a result, the device’s size, weight, and power (SWaP) values. The latest system-on-chip (SoC) device from Xilinx, the RFSoC, consists of FPGA fabric with Arm processors, analog-to-digital converters (ADCs), and digital-to-analog converters (DACs) all on the same chip.
The 16-nm technology has over 4.2K DSP slices, four 1.5-GHz A53 Arm processors, two 600-MHz R5 ARM processors, eight 4-GHz, 12-bit ADCs, and eight 6.4-GHz, 14-bit DACs per device. This game-changing technology can be used by COTS manufacturers to provide multichannel, SDR transceivers for engineers developing 5G radio products.
Figure 1 shows a functional block diagram of one COTS implementation of the Xilinx RFSoC—it’s the central component of the 5950 3U VPX board from Pentek. The “gray” area is a fully connectorized RFSoC or system-on-module (SOM) that plugs into the 3U VPX carrier. This device can be controlled via the Gigabit ENET port similar to the previous-generation FPGA. However, the on-board Arm processors allow for autonomous operation and the ability to communicate with, or control devices locally on, an external network.
1. Xilinx’s RFSoC is the central component of the Pentek 5950 3U VPX board.
Previous-generation FPGAs were programmed using a textual hardware description language, or HDL like Verilog, or VHDL. The latest AXI4-compliant IP blocks are included in Vivado from Xilinx. The IP Integrator tool from Xilinx has virtual graphical blocks that represent HDL code, which can be connected to one another via drag-and-drop wiring. Figure 2 shows VHDL code on the left in contrast to the graphical block representation on the right.
2. The Navigator FPGA Design Kit (FDK) graphical block representation (right) provides better insight than the VHDL code (left).
This more intuitive way to program enables someone new to FPGAs to wire together logical blocks that represent hardware like FIR filters and DDCs to create an SDR. Such a programming method supports fast integration of vendor-supplied, hardware-specific IP blocks with Xilinx IP blocks to create a working SDR system. Both IP block types can be combined to create a common library.
These IP programming advances provided an opportunity for COTS vendors to create a single board-support-package (BSP) module that corresponds to one IP module with all of the necessary FPGA program parameters in one location. An example would be a “Clock Control BSP Module” that corresponds directly to a “Clock Control IP Module.”
5G Application-Specific Example
Figure 3 illustrates the difference between a distributed and centralized radio area network (D-RAN and C-RAN). The traditional D-RAN “cell sites” were initially being replaced by newer C-RANs to improve data-transfer efficiency and reduce radio costs, but the latest 5G millimeter-wave massive-MIMO applications require the separation to move the remote radio head (RRH) closer to the end user because of increased RF path loss.
3. The distributed radio access network (D-RAN) utilizes an IP backhaul connection, unlike the centralized radio area network (C-RAN).
Figure 4 is a functional block diagram of a C-RAN, which consists of a baseband unit (BBU), RRH, GPS time and frequency reference, and an interconnect module. The selections in blue are possible COTS SDR locations. The BBU is located at a central office, or it’s a virtual network (“the cloud”) with access to multiple optical data lines for backhaul, and the RRH is in an external location closer to the end user. The BBU and RRH in this fronthaul connection example can use a common public radio interface (CPRI), open base-station architecture initiative (OBSAI), or standard Ethernet depending on system requirements. New fronthaul concepts like extensible radio access networks (xRANs) and open radio access networks (oRANs) will be replacing these legacy interfaces in the future.
4. A centralized radio area network (C-RAN) consists of a baseband unit (BBU), remote radio head (RRH), GPS time and frequency reference, and an interconnect module.
The various transfer-mode options combined with legacy cellular, 5G TF (Verizon specification), or the 3GPP 5G NR (New Radio) can be configured to form a complex heterogeneous network that will require a flexible development platform.
COTS Hardware Solution Example
Figure 5 is an example COTS SDR board used to emulate an RRH in a C-RAN system. A subsection of the original C-RAN with the RRH is pictured on the left side and the COTS SDR RRH to the right. The blue encircled areas are equivalent. The custom modular carrier card (light green area) contains Rx and Tx amplifiers, a GPS receiver, and an O/E transceiver module. The SOM (gray area) contains the RFSoC as well as all of the connections for power management, data storage, and analog and digital I/O.
5. This COTS SDR board emulates an RRH in a C-RAN system.
The incoming RF signal from the antenna is connected to the Rx LNA via a duplexer, isolating it from high power-amplifier (PA) transmit levels, and connecting it to one ADC channel. This SOM and custom carrier combination can emulate the original RRH, provided it has the necessary IP described in the next section.
Once inside the FPGA fabric, the digital samples are decimated, frequency-selected or tuned, and filtered in the DDC. The DDC output samples can be streamed to the power-meter module for measurement and sorted in the threshold detector IP module. Subsequently, these processed samples can be streamed to the Arm processors for crest factor reduction and digital predistortion routines before being upconverted in the digital upconverter (DUC) for re-transmission. The DUC is the reverse of the DDC using frequency translation, and interpolation instead of decimation.
The digitized I/Q sample data is packetized in the digital radio for transport to the BBU via a radio data switch, much like that in the previous description of a cellular phone call. Due to the variety of channels and data-transfer protocols, it’s necessary to calculate the maximum data throughput of your signal.
Depending on the desired level of control, either BSP routines need to be created for the new IP and Arm processors, or the Arm processors in conjunction with the FPGA can be programmed to operate autonomously.
Such SDR platforms provide superior signal-integrity performance, high test repeatability, and modular assemblies that adjust to constantly changing 5G design requirements. Future 5G implementations will require many development platforms for experimentation. By using a COTS system as a starting point, it will more than likely accelerate the time to market.
The author, Bob Muro, is an Application Specialist at Pentek Inc.
