Many companies today are exploring free, open-source hardware and software as an alternative to closed, costly instruction set architectures (ISAs). RISC-V is a free, open, and extensible ISA that’s redefining the flexibility, scalability, extensibility, and modularity of chip designs (Fig. 1). Despite its rich ecosystem and growing number of real-world implementations, there are misconceptions about RISC-V that have companies holding back from fully realizing its benefits.
1. RISC-V is an open, free ISA enabling a new era of processor innovation through open standard collaboration.
Let’s take a closer look at several myths about the RISC-V ISA to better understand the technology, tools, and requirements of the architecture, and how it can be used to accelerate innovation and drive down costs.
1. RISC-V is another processor design.
RISC-V is a fixed ISA that’s open. Standard extensions can optionally be implemented, but the base ISA is frozen forever. Because the ISA is fixed, software need only be written once, and it runs forever on any RISC-V core. Innovation can be accelerated by leveraging the open ISA. Organizations are able to optimize and customize a design for their specific applications. RISC-V is to open hardware what Linux has been to open-source software.
2. RISC-V is purely for use in academia, not industry.
Numerous corporations are implementing RISC-V to monetize their cores. IP vendors such as Andes Technology, Codasip, Bluespec, and Cortus all offer RISC-V cores to be implemented in silicon. SiFive has both licensable IP cores as well as customizable silicon based on RISC-V, including a 32 bit RISC-V SoC available for sale today. Microsemi (Fig. 2), Rumble Development, and VectorBlox offer soft RISC-V cores that run in FPGAs. For example, at the fifth RISC-V conference on November 30, 2016, a full-production time-lapse camera was shown using a RISC-V core in an IGLOO2 FPGA.