The use of simulation models provides an important starting point for SoC architectural exploration, using virtual platforms to test application workloads and datasets to optimize multicore configurations. The simulation model helps create the foundation supporting virtual prototypes, enabling early software development before silicon devices are available. Imperas Software recently announced that SiFive qualified their models for the SiFive processor Core IP Portfolio, adding that the models work with most industry-standard software IDEs and debuggers.
The Imperas models for SiFive processor IP offer user, privileged, system, and debug modes, in addition to configuration options for the RISC-V vector extensions and custom instructions. The solution can deliver simulation performance of 100s to 1,000s of MIPS, and as an example, the virtual platform model of the SiFive Freedom U540 SoC with five SiFive CPU cores can boot SMP Linux in less than 10 seconds. A debug and analysis tools support multicore design tasks, including OS porting and abstractions for application development. A simulator with proprietary code-morphing simulation technology can also be integrated within other standard EDA environments, such as SystemC, SystemVerilog, and other simulation and emulation tools from companies like Cadence, Siemens EDA, Synopsys, and Metrics Technologies.
The Imperas tools provide an overview of the activities across a full multicore SoC, including interactions across the design hierarchy for core-to-core and core-to-peripherals. Offering access and control using the software under development without modification, the solution enables end-system certifications in automotive, Mil-Aero, medical, Industrial IoT, and other safety-critical high-rel applications.
“The design freedoms of RISC-V and vector extensions are changing the traditional boundaries between the software and hardware phases of SoC development,” said Chris Jones, VP product marketing, SiFive. “The Imperas models of the SiFive cores help developers with SoC architectural exploration across the full flexibility of the SiFive Core IP Portfolio, and support early software development, which is a critical factor in validating new AI solutions.”
“SoC projects are all about partnerships; hardware and software engineers working together, with a complete ecosystem of supporters,” said Phil Dworsky, Director, Strategic Alliances, SiFive. “With this Imperas collaboration, our mutual customers will benefit from the availability of SiFive qualified models that are compatible with the mainstream EDA tool flows.”
“The SiFive Core IP portfolio covers the spectrum of the RISC-V ISA, from embedded controllers, to multiprocessors supporting SMP Linux, plus the latest vector-based accelerators,” said Simon Davidmann, CEO, Imperas Software Ltd. “These are the starting points for the next generation of domain-specific devices across almost all market segments and applications. Imperas is ready to support designs featuring single-core through to many-core arrays with our SiFive qualified models.”
