Codasip announced its adoption of Imperas Software's reference designs and DV solution for the company's IP and processor verification. Codasip includes Imperas' golden reference models in its DV test benches to properly address RISC-V adoption. Codasip uses an internal instruction-accurate model, direct and random testing, and multiple technologies for processor compliance. Imperas configurable reference models support the operational workload and scale requirements to efficiently test all configurations with the ability to adapt for new RISC-V roadmap features.
“Imperas are the pioneers in simulation technology and processor verification for RISC-V,” said Philippe Luc, Verification Director Codasip. “While processor verification is not a new problem, there are many RISC-V suppliers, with customization and various levels of verification or conformance: customers are legitimately concerned about both quality and fragmentation. Codasip is very proud of our rigorous approach to verification– using Imperas as an important part of our quality process furthers extend our differentiation. The Imperas independence, reputation and technical strength provides our customers with further reassurance in our ‘best in class’ RISC-V processors,”
Simon Davidmann, CEO at Imperas Software Ltd, added, “Codasip provides the RISC-V market with a range of processor solutions that enable optimized performance for a wide range of applications. Design verification of this processor IP is fundamental to Codasip continuing to deliver the highest-quality processors as it moves to the next generation of its IP. Each additional optional feature roughly doubles the verification workload. The Imperas approach supports Codasip’s development by applying Continuous Integration/Continuous Development to a sophisticated processor DV environment by using simulation and offers an efficiency advantage without compromising optional features. Imperas and Codasip share a common vision that improved quality is essential to the success of RISC-V.”
