Check out more coverage of the 2022 Flash Memory Summit.
Microchip Technology has rolled out a family of smart memory controllers that allow CPUs, GPUs, and SoCs in the data center to connect to DDR4 or DDR5 memory over the new Compute Express Link (CXL) interconnect.
Debuting at the Flash Memory Summit, the SMC 2000 series supports up to 16 lanes operating at 32 GT/s, promising more memory bandwidth and capacity per CPU core. The chips are designed to meet CXL 1.1 and CXL 2.0 specifications, DDR4 and DDR5 JEDEC standards, and support PCIe Gen 5 data-transfer rates. The chips also support two channels of DDR4-3200 or DDR5-4800 for the purposes of memory expansion.
To learn more about how the new CXL interconnect and the SMC 2000 series fits into the modern data center, Electronic Design met with Samer Haija, associate marketing director in the data center business at Microchip.
For more information on CXL, check out these articles:
How CXL is Changing the Data Center
CXL Ushers in a New Era of Data-Center Architecture
CXL: Coherency, Memory, and I/O Semantics on PCIe Infrastructure
How PCIe 5 with CXL, CCIX, and SmartNICs Will Change Solution Acceleration
