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Qorvo rolled out the first in a new family of single-chip battery-management ICs that can carefully manage the charging and discharging of up to 20 cells in series.
The PAC22140 and PAC25140 belong to a class of chips that it calls power application controllers (PACs). They integrate all of the core building blocks of a high-cell-count battery-management system (BMS), including cell balancing, monitoring, and protection, in one chip. As a result, they save 50% more space on the PCB and cut bill-of-materials (BOM) costs 30%, said Qorvo.
Battery-management ICs are attached directly to the cells. They report on the voltage of each cell, coordinated with their temperature and current, to make sure everything is operating safely and keeping them from expending too much energy. The ICs relay the results to a BMS microcontroller (MCU) that computes the state of charge (SOC) and state of health (SOH) of the larger battery to maximize runtime in the short and long term.
The capacity of Li-ion, Li-polymer, LiFePO4, or other types of batteries supported by Qorvo’s new chips diminishes through constant use over time. Thus, each cell needs to be carefully regulated to keep it within a safe level of charge when supplying power—and being replenished.
Overcharging or undercharging could be detrimental to the battery cells. The battery can become stressed, leading to premature charge termination (which equals less capacity) and a reduction in its useful lifespan.
Digital to Analog Divide
Qorvo said the ICs unite a battery-management front end with a Cortex-M MCU, giving them all of the analog, digital, and power-management peripherals required to manage today’s high-cell-count battery packs.
The chips are targeted at a wide range of industrial, backup energy-storage, and EV systems such as electric scooters and bicycles. Such systems are all upgrading to high voltages to enable better battery life, faster charging, and smaller and lighter form factors.
The first IC in the family, the PAC22140, features a Cortex-M0 CPU clocked at up to 50 MHz with 32 kB of flash and 8 kB of SRAM. The other member of the family, the PAC25140, uses a 150-MHz Arm Cortex-M4F MCU with 128 kB of flash and 32 kB of SRAM. Qorvo said the Cortex-M MCUs are fully flash-programmable and supported by its battery-management software and firmware libraries.
The battery-management portion of the IC is configurable for 10 to 20 cells at a time to handle the high-voltage needs of new brushed, brushless dc (BLDC), and other types of electric motors. It’s also equipped with a programmable-gain differential amplifier and a pair of 16-bit sigma-delta ADCs—one for current sensing, the other for cell balancing. The 10- to 12-bit SAR ADC is used to enable safety checks on internal nodes.
The parts are powered by the 145-V buck dc-dc controller, which supports the system with a 5-V regulated supply rail up to 225 mA. A 3.3-V linear voltage regulator pumps out up to 90 mA to enable external auxiliary power rails.
The BMS typically uses a separate power MOSFET to control the charging current to the battery and interrupt the process in the event of a short circuit or other faults. It’s preferable to place the MOSFET on the positive rail in a high-side configuration. The issue is that the gate-drive voltage of the MOSFET must be higher than the supply from the charging system or battery. According to Qorvo, the ICs integrate a charge pump to supply high voltages necessary for the external charge and discharge FETs.
The devices also have a “hibernation mode” that limits power consumption to less than 3 µA, which delivers a long storage time with wakeup from pushbutton, timer, and charger detection.
The PAC22140 features a wide range of serial communications and other protocols, including UART, SPI, I2C, SMBus, and GPIOs. The PAC25140 comes with all of the same connectivity options plus the CAN bus.
They also feature short-circuit and overcurrent protection to shut down the hardware to prevent delays and stress to the battery or BMS.
A Boost to Cell Balancing
The chips incorporate cell-balancing FETs used to redistribute the level of charge in the cells. By balancing the SOC of the cells, you can prolong a battery’s remaining life and prevent damage.
Cell balancing is one of the more crucial roles of a battery-management system, even more so as a larger number of cells are connected in series in large battery packs to boost the amount of energy it can store.
Cells at the heart of a battery pack have slight differences when it comes to capacity, internal resistance, self-discharge rate, and other factors. These are largely due to inconsistencies in manufacturing. And so, at any given time in the lifespan of a battery, one cell (or small group of cells) will have less charging capacity than the other cells in the pack. As a result, the battery's performance is constrained by the "weak" cells in the system. Li-ion batteries also lose storage capacity over time due to the stress of repeated charging and discharging.
Because the battery cells are in series, they all have the same charging and load current. During charging, not all battery cells in the stack will be topped off at the same time, due to the slight imbalances in internal resistance and storage capacity. If one cell reaches a fully charged state before the others, power is cut off—even if other cells can still be charged—because faults can occur when the cells are overcharged.
During discharging, the "weak" cells also will reach empty first, even though energy remains in other cells. Depleting the SOC too deeply can damage the batteries in ways that are impossible to undo.
With passive balancing, when one cell hits its maximum SOC before other cells in the battery pack, excess energy is dissipated from the cells that filled too fast. And, in turn, others continue being recharged.
Qorvo said the chips, which will be in mass production before the second half of 2023, provide 50 mA of current for cell balancing to ensure all battery cells are fully replenished and safely depleted.
The PAC22140, which fits inside a 9- × 9-mm, 60-pin QFN package, is currently in production. The PAC25140, sampling now with production set for the second quarter of 2023, is housed in a 10- × 10-mm, 68-pin QFN package with power pad.
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