Power Supply Cuts Switching Noise In DDR Memory Systems

This design idea describes a unique, low-cost power-supply circuit for a double-data-rate (DDR) memory system. Conventional designs for DDR memories consist of a dual buck converter and a voltage reference. In contrast, this design replaces one buck converter with a linear regulator (Fig. 1). The benefit of this approach is replacing the relatively large inductor and associated switching noise of a pulse-width modulated (PWM) converter with a small, low-noise op-amp linear regulator.

DDR memories bring new challenges to the power-supply designer. They require an efficient main power source of 2.5 V (V_DD) and a termination voltage (V_TT) that accurately tracks one-half of V_DD (i.e., 1.25 V) and can both source and sink current. A third voltage is needed (V_REF) to track V_DD/2.

In this circuit, a low-voltage synchronous buck converter generates an 8-A V_DD output at 2.5 V. The V_TT and V_REF voltages are produced with an op-amp linear-regulator design. The circuit is designed for low-power DDR systems, like desktop PCs. But its output power can be increased by selecting the proper external inductor and capacitors for high-power systems like PC workstations.

Voltage V_DD powers the memory ICs and the buffer interface circuits. V_TT is used for the pull-up resistors and must be able to either sink or source current. To save power, V_TT is equal to V_DD/2 instead of V_DD. The power dissipated in the resistors equals the voltage squared divided by the bus resistance. So a termination voltage of V_DD/2 yields a factor-of-four power savings. The third voltage is implemented as a reference voltage to the differential-amplifier input section of the receiver ICs.

The 2.5-V V_DD supply uses an ON Semiconductor NCP1571 low-voltage synchronous buck controller. The controller contains the required circuitry for a synchronous N-channel MOSFET buck regulator with a 200-ns transient response, an output regulation of ±1%, and a fixed internal frequency of 200 kHz.

As mentioned, the V_TT supply is the same as one-half of the V_DD voltage, or approximately 1.25 V. Op amps U2a and U2b function as voltage followers to create V_TT. The input to U2b comes from the resistive voltage divider formed by R5 and R6. This splits the 2.5-V V_DD supply in two to form the V_REF reference voltage. Also, U2b provides filtering to remove any high-frequency switching noise produced by the synchronous buck converter. The V_TT output—formed by U2a and transistors Q3 and Q4—tracks the voltage at the noninverting terminal by virtue of its voltage-follower circuit configuration. Thus, the V_TT supply's output voltage is referenced to 50% of the 2.5-V V_DD supply, rather than an absolute 1.25-V reference.

The sink and source feature of the V_TT supply is provided by MOSFETs Q3 and Q4, which extend the current capacity of the basic op-amp circuit. When the V_TT supply is in the current-sinking mode, Q3 is "OFF" while Q4 is "ON." The output of U2a will be at a negative voltage to control the V_GS of the P-channel MOSFET (Q4) to maintain the V_TT voltage of 1.25 V.

In a similar manner, when the V_TT supply is sourcing current, Q3 is "ON" and Q4 is "OFF." The output of U2a will reach a positive voltage to control the V_GS of the N-channel MOSFET (Q3) to maintain the 1.25-V V_TT. Resistor R7 isolates the output of U2b from V_TT and the bulk capacitor, C15. In addition, R7 provides negative feedback to reduce the output resistance of the V_TT circuit.

V_DD, V_TT, and V_REF were measured at 2.458 V ±0.015 V, 1.224 V ±0.008 V, and 1.225 V ±0.008 V, respectively. The load range was no load to 8 A for V_DD, and ±2 A for V_TT. The efficiency is about 80% for a V_DD current load greater than 2 A (Fig. 2). Figure 3 shows the steady-state V_DD and V_TT ripple voltages.