The general-purpose current source in Figure 1 is accurate within 1% and insensitive to temperature (less than 50 ppm/°C). It also has a high output resistance and a wide compliance range (4.3 to 34 V). This composite configuration uses an IC voltage reference (IC1) and resistor (R1) to create a current source that follows the expression ISOURCE = VREF/R1 + IC1's ground current.
IC1's accuracy is extended beyond its 5.5-V supply-voltage limitation (CMOS). This is achieved using a bootstrap integrator made by IC2, R2, and C2, which keeps IC1's input within compliance. Consequently, a precise current source that matches the wide supply range of IC2 is produced.
IC2 is the pass device that keeps IC1's input within compliance (below 5.5 V). With the bootstrapping of IC2, this configuration doesn't have an additional IC2 ground-current error. IC2, R2, and C2 form an integrator that forces IC1's input to keep the voltage across R1 equal to VREF. At the same time, IC2's output sources current through R4. This current sums with IC2's negative supply current. ISOURCE is generated by this current through R1 plus a small IC1 ground-current offset error (50 µA).
The error in accurately setting ISOURCE with this composite configuration is derived from three sources. VREF and R1 are both available in 0.1% tolerance. IC1's ground-current variation of ±7 µA on 50 µA translates to an additional 0.2% tolerance. When these tolerances are combined, the total ISOURCE tolerance is under 1%.
Similarly, ISOURCE's insensitivity to temperatures from −40°C to 85°C is a function of the temperature coefficients of VREF, R1, and IC1's ground current. The LM4130 is available in a 0.1% tolerance with 20 ppm/°>C TC grade. Inexpensive resistors are commonly available in 0.1% tolerance with 25 ppm/°C TC grade. The LM4130's ground-current variation of ±5 µA on 50 µA over temperature provides an additional TC of 20 ppm/ÅC. Therefore, the total ISOURCE TC is lower than 50 ppm/°C.
C1 enables startup of the configuration from a VSOURCE power-on step. With this choice of C1, the startup delay-time is 100 ms from a 5-V step. For a fast-edged VSOURCE, a 1-ms startup can be obtained by using a 0.001 µF cap for C1. R3 is used to isolate VREF from the integrator during startup. R4 level-shifts IC2's output (which is IC1's input) up above VREF, while R5 current limits IC1's input during startup.
IC2 was selected because of its wide supply range and input common-mode range, which includes its negative supply. The typical ground current of IC2 (0.6 mA) restricts the lowest setpoint for ISOURCE. IC2's maximum output current (10 mA) limits the highest setpoint for ISOURCE.
Figure 2 shows ISOURCE versus voltage with an output resistance greater than 10 M(omega). The compliance voltage is from 4.3 V to 34 V. This upper margin is the maximum IC2 compliance plus VREF. The lower limit is the minimum IC2 compliance plus VREF.
