Example 4: This paralleling technique using the sensing circuit as shown in Figure 5 has been demonstrated with a dual-phase, voltage-mode controller (LM2647) to combine 30-A, 1.2-V channels into a single 60-A output without introducing added loss.
Two channels are configured as shown in the simplified diagram of Figure 5 using four DPAK FETs. The switching frequency is 335 kHz, L1 = 0.85 m H, COUT1 = 1000 m F for each channel.
With the phases shorted together, the current-sharing loop becomes active as evidenced by the output voltage of U2 coming off the rail and settling near the IC reference voltage. Test results demonstrate good current matching as evidenced by a measured temperature differential of less than 2°C between any of the four 3717 FETs—at a fullload current of 60 to 80 A.
Efficiency measurements for each channel alone matched the combined efficiency, ranging from 89% at 20 A to 81% at 80 A (Fig. 6). Step response waveforms for 1/2 full-load steps were indiscernible when comparing single channels to combined channels.
Although the preceding example assumed VIN for each channel is the same and the desired current-sharing ratio is unity, this may not always be the case. Power can be summed from different rails to keep from overloading a single VIN. Simply adjusting the gainsetting resistor ratios around the U1 amplifiers can accommodate this requirement. Varying one channel gain with respect to the other causes the
sharing-current ratio to vary inversely to the gain. One can see the advantages gained from paralleling two channels in the graphed data (Fig. 6, again). The total loss for each channel at a load of 80 A is about 11 W. But for 40 A it is only 3.5 W. This shows a 4-W power saving by paralleling two channels at 20 A/channel compared to one channel supplying 40 A.
