Cascode Configured GaN Switch Enables Faster Switching Frequencies And Lower Losses
Most of us have seen some incredible innovations in the world of power electronics. It’s hard to cite where “Mark Twain” is in the river of power semiconductors. But if we simply pick the 2N3055, a 60-V VCEO, 15-A NPN transistor, that seems like a good safe “depth” on the proverbial leadline. When we needed a few more fathoms of the state of the art, we could cascode higher VCBO bipolar junction transistors (BJTs) with lower-voltage MOSFETs, and I’ve seen some true genius in that arena.
The industry is now several generations into superjunction MOSFETs that have good figures of merit; RDS(on) in particular is low compared to predecessor silicon FETs. Presently, this is “safe passage” for many power electronics designs. But it’s only traded against increasing pressures to make stuff smaller, faster, and more efficient.
As innovation steams on with time, we can’t help but wonder where the next stop will be along this river. The answer lies in new higher-mobility semiconductor materials—gallium-nitride (GaN) devices, or more specifically, cascoded switches with GaN high electron mobility transistors (HEMTs) as the upper element.
Some Background
Phil Nowaczyk, a great engineer and a good friend from Zenith Electronics, first introduced me to cascoded devices in the switched-mode power supply (SMPS) world in the mid-1990s. As Phil took me through the schematic for his high-speed raster scanned deflection circuit, we got to the horizontal section.
Back then, a typical horizontal section had a low-gain BJT with very high VCBO and novel base drive circuits comprising things like Baker clamps and proportional base drive to keep from pounding the device too far into saturation. They often had a copack diode across the CE terminals.
This was fairly familiar to me. But when we got to the horizontal section in Phil’s schematic, I saw something entirely different. I saw a BJT sitting on top of an N channel MOSFET! I didn’t understand this at all. It took a good long stare and some good old-fashioned thinkin’ to figure out how that worked.
The summary from Phil was entirely correct, and it was very likely over-condensed to invoke thought, reasoning, comprehension, and perhaps even deep storage. Phil is a genius that way.
Rather than blowing hot air on the print for three hours and hand waving, he summarized, “The MOSFET switches the current. The BJT switches the voltage,” which was nothing short of marvelous. With this cascode, he was able to switch the BJT much faster than he could with a single device and the aforementioned base drive tricks.
On The Bench
The cascode was needed because this particular project was for a new system that had 1080 vertical lines, compared to well proven deflection systems with 525 horizontal lines. The vertical refresh rate had remained at 30 Hz (interlaced), so the horizontal sweep needed to run at 32.4 kHz. The currents were also much higher due to the higher luminous output of the projector. The best BJT we had at the time couldn’t do it alone.
This particular cascode made the BJT look like a common base amplifier when it was in the ON state. The VCE drop across the device was held minimal by selecting the proper drive current. When the lower MOSFET turns off, it disrupts the base drive current path to the BJT in addition to the primary current in the transformer. It is dubbed the “switched emitter” for obvious reasons.
The BJT/MOSFET cascode faces a bright future. The downside is that it’s a compound device that requires a supply for the upper element and drive for the lower MOSFET. Some will dismiss it since it’s not in the dogmatic SMPS design textbooks that we are all accustomed to. However, I don’t see it as a reason to hide under the bed.
The added circuitry can control a lot more than switching speed. The downside of this cascode lies in the reverse current flow. For example, if we used this switch in a half bridge with an inductive load, there is no real fast recovery epitaxial diode (FRED) built in. We can surely add one, but it’s no more or less lossy than any other high voltage PN-junction FRED (Fig. 1).
1. One disadvantage of a switched emitter BJT/MOSFET cascode is that requires a supply for the upper element and drive for the lower MOSFET.
Clearly the concept of a cascode has been around for a long time in both linear and switch-mode circuits. Some may recall the use of cascoded vacuum tubes or BJTs in various high-speed linear applications, perhaps a good audio pre-amplifier or a rework of an old Dynakit.
The most recent addition to the cascode family comes from International Rectifier. It consists of a 600-V, III-V device on top and a low-voltage silicon MOSFET on the bottom. This device works a little differently than a switched emitter.
The IR device embodies a GaN HEMT as the upper element. On its own, this GaN HEMT is in the ON state when its gate-source voltage is at 0 V and in the OFF state when the gate source voltage is at –8 V or so. Clearly this would be difficult to build an offline converter with on its own given that virtually all pulse-width modulation (PWM) controllers run from a positive voltage source and deliver a “high” state pulse as “ON.”
This is where the cascode comes in. By placing a low-voltage, enhancement mode N channel device under this element, I can tie the gate of the upper GaN HEMT to the source of the lower MOSFET, thereby the VGS of the upper device is the negative of the VDS of the lower MOSFET. It’s a bit confusing, but once you reason through it once or twice it makes sense.
When the low-side MOSFET opens up and the voltage across the device rises, it applies this voltage to turn off the GaN HEMT. When the low-side MOSFET turns on, the upper cascode turns on as a response to the VDS of the lower devices dropping to very low voltage. In this embodiment, we only need to consider it as a three-terminal device. The midpoint of the cascode is embedded, as is the upper gate to lower source connection (Fig. 2).
2. With this low-voltage N-channel GaN cascode arrangement, it’s possible to tie the gate of the upper GaN HEMT to the source of the lower MOSFET, in which case the VGS of the upper device is the negative of the VDS of the lower MOSFET.
Old Versus New
In applications, there are several differences between the N channel MOSFETs and the GaN cascoded switch. And if we take a close look at the turn-on event of a standard MOSFET compared to the GaN cascoded device, we see some noteworthy differences.
The way a standard MOSFET works at turn-on is pretty straightforward. It’s old hat for most of us, but is worth a review. As we ramp VGS from 0 to 12 V or so, we first pass through the threshold voltage of the device, VTH. This happens at t1 in Figure 3. At this point, the drain current, ID, is measurable. The voltage drop across the device has not changed.
3. Recalling the turn-on of a standard MOSFET, VGS passes through the threshold voltage of the device at t1. Between the threshold and the onset of the miller plateau (t1 to t2), CGS accumulates charge and ID is ramping up. At t2, ID is at maximum and VDS is still at full blocking. At this point VDS begins to fall rapidly. By (t3), VDS is at the minimal voltage dictated by ID*RDS(on) and the MOSFET is saturated. Most of the switching loss is due to the time between t2 and t3. See the text for implications.
From the threshold to the onset of the miller plateau (t1 to t2), the gate-source capacitance is accumulating charge and the drain current is ramping up. At the onset of the miller plateau (t2), the drain current has hit its maximal value and the drain source voltage, VDS, is still at full blocking. VDS then begins to fall rapidly. By the end of the miller plateau (t3), VDS is at the minimal voltage dictated by ID times RDS(on). The MOSFET is saturated at this point.
The time spent in the miller plateau is the dominant contributor in the switching loss of the MOSFET. Most gate drive circuits wish to minimize this, though it’s traded against di/dt impact on radiated and conducted noise from the device and associated conducting loops.
It is noteworthy to mention that adding a small amount of external capacitance to the gate source terminals only increases the RC time constant of the total gate drive resistance and the gate-source capacitance. So, added incremental gate capacitance does not impact the miller plateau or the time spent getting through it. Rather, it impacts the di/dt between t1 and t2.
IR’s GaN cascode works a little differently. From t0 to t1, the gate-source voltage of the MOSFET ramps up to the threshold of the MOSFET (Fig. 4). As VGS climbs higher, we enter the miller plateau of the MOSFET at t2. At this point, the VDS of the MOSFET is still high. The upper GaN HEMT, then, is still in the off condition.
4. When the GaN cascode turns on, from t0 to t1 the MOSFET’s VGS ramps up to its threshold and enters the miller plateau at t2. At this point the VDS of the MOSFET is still high and the upper GaN HEMT is still off. From t1 to t2, the MOSFET’s VDS begins to drop. At t3, the VDS of the MOSFET drops to the threshold of the upper GaN HEMT, which begins conducting rapidly. Between t3 and t4, the upper GaN HEMT transitions to its ON state.
As we traverse the miller plateau, the VDS of the MOSFET begins to drop. (Remember, the VDS of the MOSFET is the negative of the VGS of the upper GaN HEMT!) At t3, the VDS of the MOSFET drops to the threshold of the upper GaN HEMT. At this point the upper GaN HEMT begins conducting rapidly, since it’s a high-transconductance device with minimal capacitances. Between t3 and t4, the upper GaN HEMT transitions to its ON conducting state.
Another Look
It might be a little easier to see if we look at it a different way. Let’s look at the upper GaN HEMT as a common gate amplifier or a level shifter. As the low-side device turns on, the upper device actively collapses its own drain source voltage. Only in the case of the IR GaN HEMT, this happens rapidly as the capacitances and total gate charges of the upper GaN HEMT are much smaller than their counterparts in a comparable high-voltage superjunction MOSFET.
If we think back to linear circuits and cascoded elements, when we needed more speed from a given device, we set it up in a cascode. In that arrangement, the upper active element reduced the miller capacitance of the lower element by actively swinging in the desired direction.
Some viewed the upper element as a common base level shifter. By adding this upper element, a speed enhancement could be realized for the cascoded combination. Switching circuits are similar in this regard, only we seek to spend minimal time in the active region.
If we look at the switching waveforms for the cascoded device, we can see minimal miller plateau and the level shifting effect of the upper GaN HEMT. Since the low-side element is a low-voltage MOSFET, the on-state performance of the cascode only has a small penalty added for the added element. The low-side device is kept to less than 10% RDS(on) contribution in most cases. During turn-off, we see attributes that are again in line with the higher switching speeds offered by the cascode (Fig. 5).
5. Turn-off waveforms for the GaN cascode and MOSFET illustrate the switching speed advantages of the cascoded device.
One advantage of this particular cascode becomes clear upon detailed inspection. When the intrinsic body diode in the low-side device conducts, the gate source terminals of the upper GaN HEMT raises above the (negative) threshold and well into the saturated ON state. The upper GaN HEMT is saturated ON at this point as well. This means the overall freewheel current path will flow through the intrinsic body diode of the low-side MOSFET and the upper GaN HEMT.
Recall that the intrinsic body diode in the low-side, low-voltage MOSFET is much faster than a high-voltage body diode and also has a much lower QRR. In fact, the QRR rivals silicon-carbide diodes.
What’s Next?
This is a brief look at the nuts and bolts of how IR’s GaNPowIR technology works when operated in cascode configuration. The cascoded low-voltage silicon FET/high-voltage GaN HEMT switch offers dramatically improved performance (with an R times Qoss figure of merit that’s four times lower than silicon devices!) and rectifier performance similar to SiC diodes.
The cascoded device behaves like a traditional enhancement mode MOSFET with dramatically increased speeds and ”body diode” performance. Their lower charge results in much lower switching loss, which allows SMPS designers to build switching converters that operate up to four times faster than the switching frequencies that we are used to now at efficiency parity. The gate drive voltage requirements of the cascode are determined by the gate oxide of the low-voltage MOSFET, which is to say it can be easily driven with existing low-cost circuits and drivers.
This brief description is by no means a complete work designed to get engineers ready to be turned loose on the bench with IR’s GaNPowIR devices. We need to discuss the design “care abouts” of the devices, high-speed layout techniques, packages, and design for EMC. These discussions will come with time.
Tangential to some wisdom that Phil Nowaczyk once imparted, I’d rather do the work on the bench, back it up with some stats, and then explain it to my fellow engineers to avoid verbal entropy as he did with me once upon a time. Now all we have to do is to get the magnetics people working on nanoscale strings of iron molecules for high-flux, low-loss core materials into the megahertz regions! Wouldn’t that be nice?