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    1. Technologies
    2. Power

    The Future Of Power Efficiency

    Feb. 18, 2013
      Roundtable with execs at CUI Inc., N2Power and XP Power about power supply efficiencies beyond the mid 90s.

    While upgrading the grid and repowering the data center are grand, sweeping issues, it’s important not to lose sight of basics. For an international perspective, we discussed future efficiency gains and advances in digital power with senior executives at European power supply companies: Jeff Schnabel, VP of marketing at CUI Inc.; Don Knowles, VP of engineering at N2Power; and Gary Bocock, technical director at XP Power.

    Don Tuite: The efficiency of medium size ac-dc power supplies is now firmly in the mid-90% area. And while these efficiencies are impressive, the vast number of power supplies shipped each year means even small efficiency gains have a significant effect on our power consumption. Where do manufacturers go from here, and what limitations are in place?

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    Don Knowles: We see potential gains in four basic areas: interconnections, with their parasitic resistance and inductance, as well as copper and energy losses in the inductor; power components and topology; selection of semiconductors, such as enhancement-mode gallium-nitride-on-silicon FETs and SiC (silicon-carbide) diodes; and better magnetic components, with lower-loss core material.
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    Gary Bocock: In many ac-dc power supplies, the bridge rectifier generates the biggest single power loss. This is a low-cost, low-technology, reliable component, and replacing it with a more efficient solution is more complex and expensive. There are products that use bridgeless PFC (power factor correction) designs, though this tends to be limited to higher-power, higher-cost products. Higher-power products also utilize interleaved PFC designs, significantly reducing the losses at low line input and reducing stress on the bulk storage capacitors.
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    Jeff Schnabel: I believe that tomorrow’s innovations will occur through the discovery and implementation of new power topologies and materials such as gallium nitride (GaN) and silicon carbide. As an example, CUI’s [dc-dc] Solus Power Topology currently is able to reduce switching turn-on losses by 75% and switching turn-off losses by 99% on the control FET when compared to a conventional buck converter. Our testing shows that it holds similar advantages when implemented in ac-dc, ultimately allowing for increased efficiency and reduced package size.

    DT: How much of an improvement will we see during 2013, and what’s likely in five years?

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    JS: We see that the biggest short-term gains in power supply efficiency, overall, rather than peak, will come as a result of reducing power consumption at the no-load end of the curve, i.e., when the device is in standby. We’re not alone, however, and the regulation bodies have begun to make this a priority. Along with the introduction of new topologies, digital control in ac-dc supplies will also have a significant effect over the next five years, allowing for greater power supply and power system optimization.
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    DK: We’ll see an increase of one to two percentage points in efficiency in 2013 and two to three points in the next five years, along with improvements in power factor correction performance over a broader range of ac-line inputs. Perhaps most dramatically, the increased use of digital control loops—not just digital supervision of analog loops—will change performance levels, improve PFC, add flexibility, enable the supply to adapt to varying and complex line and load situations, and offer increased real-time reporting on the supply’s operation and internal parameters.
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    GB: The latest designs include quasi-resonant PFC stages, resonant power converters, and synchronous rectification to minimize the switching and other losses throughout the power chain. New products reach efficiencies of 95% at high line input voltages and maintain efficiencies above 92% at minimum input voltage. The development of components and techniques will see this improve.

    DT: What are the biggest challenges faced in improving system efficiency through power supplies?

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    GB: It is important to focus on low line efficiency and cost-effective methods for reducing power dissipation in the rectification and power factor correction stages. Market price remains a key driver, especially for lower-power products, as the cost of small efficiency improvements can be prohibitive. Continuing to reduce the size of products has an adverse effect on increasing efficiency and on product lifetime.
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    JS: The biggest challenge resides in the fundamental nature of switching conversion and the associated switching losses at turn-on and turn-off. The never-ending challenge of power supply designers will be to minimize these losses, whether through topology breakthroughs or component-level improvements.

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    DK: Current levels are increasing, so contact and lead resistance, internal IR drop, and related basics are becoming more severe. Operating the supply at a higher internal voltage is part of the answer for increased efficiency, but this brings new creepage, spacing, and safety issues. Increasing the frequency of operation will reduce size but not efficiency, due to increased core losses in magnetics and increased switching losses in the semiconductors.

    DT: What are the key factors OEMs should specify if they are to improve the system efficiency through the power supply?

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    DK: First, don’t oversize the supply for insurance headroom. If you run the supply at much lower loads than this zone, you’ll actually be operating in a very inefficient region. Second, try to avoid active (forced air) convection cooling using fans since they waste power, add noise, and reduce reliability. Instead, use an efficient supply, properly sized, and mount it so unforced convection and conduction cooling will keep it within its rated temperature.
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    GB: The key is to look at power supply efficiency in the operational area of use, i.e., look for the detail rather than the headlines. If the equipment will be used throughout the global market, then the efficiency at low line is more interesting that the headline efficiency at 230 V ac. The load drawn in the application is important as products often offer their peak efficiency at higher percentage loads. There is a tradeoff between efficiency, size, and cost, which drives the product design.
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    JS: Because real-world systems typically do not operate at a steady state, OEMs should examine the power supply’s complete efficiency curve and ensure it is optimized to their application’s loading profile. By doing so, they can best match the power supply to their system’s needs. 

    About the Author

    Don Tuite

    Don Tuite writes about Analog and Power issues for Electronic Design’s magazine and website. He has a BSEE and an M.S in Technical Communication, and has worked for companies in aerospace, broadcasting, test equipment, semiconductors, publishing, and media relations, focusing on developing insights that link technology, business, and communications. Don is also a ham radio operator (NR7X), private pilot, and motorcycle rider, and he’s not half bad on the 5-string banjo.

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