Topology Selection by the Numbers-Part One

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Is the topology you selected for your current power supply design the best topology available? Often, there are several different approaches we can take to a power design challenge. This three-part article looks at some tools that can help the engineer make better power design choices. In this first part, a new analysis method that enables comparison of different power conversion topologies will be defined and we'll apply this tool to two simple topologies.

Called component stress factor (CSF), this new method is intended to allow an apples-to-apples comparison of topologies, providing numerical scores for each component type in each topology for a specific set of operating conditions. To be effective, CSF should correlate well with actual power loss in the component and provide information that can be used for design optimization.

CSF must be distinguished from an existing method for direct numerical comparison of power converter topologies. The existing method is based on the concept of component load factor. B. Carsten defined this concept in a paper presented at the 1988 PCIM conference held in Munich, Germany. The paper, “Converter Component Load Factors: A Performance Limitation of Various Topologies,” also provides some examples of component load factor as well as some results and general conclusions.

The differences between component stress factor and component load factor lie in how the individual and total component factors are calculated and in the results achieved. In the new method, we require that all of the candidate topologies have available exactly the same amount of silicon, magnetic winding area and capacitor volume. We calculate three different CSFs.

For semiconductors, we calculate a semiconductor component stress factor (SCSF); for magnetically inductive windings, we calculate a winding component stress factor (WCSF); and for capacitors, we calculate a capacitor component stress factor (CCSF). After calculating a CSF for each component, we sum component factors of the same type. Therefore, we get these three sums:

In general, we have an operating condition that specifies a range of line voltages. Good design practice requires designing for the worst-case conditions, because reliability is a primary goal. It makes sense to calculate a worst-case total CSF for each component type and compare optimal worst-case sums for different topologies. We calculate total CSFs for each line-voltage extreme as well as total worst-case CSFs for each component type, forming these sums:

where SCSF_{WORST_i} is the worst-case SCSF for transistor i, WCSF_{WORST_i} is the worst-case WCSF for winding i and CCSF_{WORST_i} is the worst-case CCSF for capacitor i.

In the CSF method, we give each component a weight that indicates the amount of resources to be assigned to the component. We form a sum of component weights for each component type and divide the sum by the individual component weight to form a weighting factor for each component:

where W_i is the individual weight assigned to component i and Σ_jW_j is the sum of the individual weights for all components of the same type in the circuit. For starters, we assign W_i=1 for each component, and later on we can adjust the individual component weights to optimize the results.

A component's stress will depend on the maximum applied voltage as well as the maximum current in the component. We will want the component stress to correlate well with the power dissipated in the component. For a MOSFET, the conduction loss is equal to the square of the RMS current times the channel on-resistance. For a given die size, the channel resistance is proportional to the square of the voltage rating. Higher voltage rating implies a longer channel with smaller cross-section, which yields the dependence on the square of the voltage rating. We define the semiconductor CSF to be:

where SCSF_i is the individual transistor's CSF, V_{MAX_i} is the maximum peak voltage applied to the transistor, I_{RMS_i} is the maximum RMS current in the transistor, and P is the total power processed by the circuit, assuming the converter is 100% efficient. The inclusion of P in the definition of CSF normalizes the CSF by removing any dependence on the power processed and makes CSF a dimensionless quantity.

In our calculations of RMS current in this article, we will assume that the circuit's inductors are large and there is no variation in the current during the operating states of the circuit. We can calculate the RMS current from:

where Dⁱ is the duty cycle of the i^th operating state, and I_i is the transistor current during the i^th operating state.

For magnetic components, we will assume that each circuit has available exactly the same amount of window area for windings. We will treat each winding as a separate component, assigning a weight to each winding and then calculating a CSF for each of them. First, we define a CSF for windings:

Conduction losses in a winding are joule heating losses, or I²R type losses, so we can readily see why we need to include I²_{RMS_i} in the definition. I²_{RMS_i} is calculated in the same way as indicated previously for transistors. In order to accommodate applied voltage in a magnetically inductive element, we need turns of wire in proportion to the voltage. More turns of wire mean less window area available for each turn and a longer wire. The winding resistance will be proportional to the number of turns and inversely proportional to the cross-sectional area available for each turn; therefore, the winding resistance will increase with the square of the number of turns, which will be proportional to the voltage squared. We calculate V_{MAX_i} using this formula:

under worst-case conditions for the winding (i.e., the condition that yields the largest value for V_{MAX_i}), where D_i is the duty cycle of the i^th operating state of the converter under the worst-case condition and |V_i| is the absolute value of the winding voltage in the i^th operating state.

For capacitors, we calculate CSF in much the same way. We assign a weight to each capacitor in the circuit. We determine the peak voltage stress for the capacitor and calculate the RMS current in the capacitor. We reason that the stress in the capacitor is primarily due to joule heating; therefore, we want the CSF to represent a joule heating loss, or I²R loss, where R represents an equivalent series resistance (ESR) in the capacitor, which means that the CSF for capacitors will depend on the square of the RMS current in the capacitor.

Generally, ESR is a function of the volume of a capacitor. The volume of a capacitor is proportional to its energy-storage capacity, 1/2C × V², so that the component stress for the capacitor also depends on the squared peak voltage of the capacitor. For capacitors, we define the CSF to be:

Some circuit approaches combine topologies. We can enforce the equal resource rule by giving each subconverter a weight for each component type and forming new CSF sums for each candidate topology, where we add up the CSF sums but also give each subconverter a weight for each component type. For the total SCSF for a combination of subconverters, we define:

where W_i is the semiconductor subconverter weight for subconverter i, Σ_{SEMICONDUCTORS} is the sum of the semiconductor subconverter weights, and total SCSF_i is the total SCSF for subconverter i.

We calculate winding and capacitor CSFs for the subconverter combinations in the same way, but the subconverter weights for windings and capacitors may be different than the semiconductor subconverter weights. In general, we will assign a weight of 1 to each subconverter and later on make adjustments to the weights, to accomplish design optimization by assigning resources where they are needed most to reduce total worst-case CSF.

In the buck converter of Fig. 1, assume that the input voltage is 200 V, the output voltage is 100 V and the load is 100 Ω or 100 W. Let's give each MOSFET a weight of 1 for now, which suggests that we intend to make each MOSFET the same die size. For M_MAIN the maximum voltage stress V_{MAX_MAIN} is 200 V. We can calculate the RMS current to be:

We can plug the values we know into the formula for SCSF to find the SCSF for M_MAIN:

For M_SYNC, the maximum voltage stress is 200 V and the RMS current in M_SYNC is the same as in M_MAIN. We calculate the SCSF for M_SYNC to be:

Now we can calculate a total SCSF for the Fig. 1 circuit:

We can calculate a winding CSF for the buck choke and set the weight of the buck choke to 1. The current in the buck choke is a constant 1 A and the voltage magnitude is always 100 V; therefore:

Since there is only one winding, the total WCSF is also 1.

We have two capacitors in Fig. 1. We will assign a weight of 1 to each of the capacitors and calculate CCSFs. The peak voltage of the input capacitor is 200 V. The average current into the capacitor is 0.5 A. During the on-time of the main switch, there is a net current of 0.5 A out of the input capacitor, and during the off-time of the main switch, there is a net current of 0.5 A into the input capacitor, so that the magnitude of the capacitor current is always 0.5 A. For the output capacitor, the input current to the capacitor is always equal to the output current from the capacitor so that the net current in the output capacitor is zero:

Now that we see how to calculate CSFs, we can calculate CSFs for the buck converter for a variety of line-voltage conditions. In each case, the load is the same. The results are summarized in Table 1.

In the last case illustrated in Table 1, where the line voltage varies over a wide range of values, we calculate worst-case CSF sums assuming equal component weights. At the low line-voltage extreme, all of the semiconductor stress is in M_MAIN, but at the high-voltage extreme, almost all of the semiconductor stress is in M_SYNC. For comparison purposes, we need to calculate total worst-case CSFs. For the wide line range case:

If we assign unequal weights in order to achieve lower total CSFs, we find that we can improve the situation only slightly for the semiconductors. However, the CSF of the output capacitor in a buck converter is zero using our assumption that the inductor values are large, which implies that the inductor current is invariant. In this case, we can assign additional capacitor resources to the input capacitor and reduce the assignment to the output capacitor. The optimal results are shown in Table 1.

Two key points to remember about the buck converter are: the total SCSF for equal component weights is invariant over the line range, and the total SCSF for equal component weights is proportional to the square of the ratio of maximum line voltage to output voltage.

In the Fig. 2 boost converter, the input voltage is 500 V, the output voltage is 1000 V and the load is 100 W for 10 kΩ. For each switch, the weighting factor is 2, the voltage stress is 1000 V, the current stress is (√2)/10 A and the SCSF is 4, so that the total SCSF is 8. For the choke, the weighting factor is 1, the voltage stress is 500 V, the current is 0.2 A and the WCSF is 1.

If we assign equal component weights to the capacitors, the input capacitor will have a current of 0 A so it will have a CCSF of 0. For the output capacitor, the weighting factor is 2, the voltage stress is 1000 V, the current is 0.1 A and the total CCSF is 2. If we optimize the capacitor weights to achieve the lowest total CCSF, we would assign a weight of 0 to the input capacitor, which would yield a total CCSF of 1. In Table 2, we summarize some results for a variety of line-voltage conditions. In each case, the load is 1000 V and 100 W.

There are some key points to remember about the boost converter. Firstly, the CSFs are similar to the buck converter for the cases in which the line voltage and load voltage are fixed. Secondly, in the case where the line voltage varies, all of the CSFs are highly line-voltage dependent, becoming small — compared to the buck converter — at nominal and high-line voltages.

Thirdly, in the variable line-voltage case, optimal worst-case total SCSF is much lower than the buck converter while the worst-case total WCSF is much higher than the buck converter. For the boost choke, the worst-case voltage stress occurs where the duty cycle is 50%, or if the duty cycle is never 50%, then the worst case occurs where the duty cycle is closest to 50%. And lastly, the worst-case total SCSF for equal component weights is proportional to the square of the ratio of the load voltage to the minimum line voltage.

In most situations where you would consider a buck converter, a boost converter would be an unlikely alternative; however, where you cascade a stage of regulation with a dc transformer, then either could be candidates for the regulation stage. Which would be the better choice?

In the next part of this article series we will look at some nonisolated topologies that are attractive alternatives to simple bucks and boosts for some applications.

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