Point-of-Load DC-DC Regulator In New Versions

Ericsson has added two 3E* DC-DC regulators to its family of BMR461 12 x 12 x 8 mm digital point-of-load (POL) modules. The two new variants in the BMR461 family offer current outputs of 6 A (BMR4612001) and 18 A (BMR4614001) and join the existing 12 A version (BMR4613001) launched toward the end of last year. Like the 12 A BMR461 regulator, these two new modules also deliver Dynamic Loop Compensation (DLC), advanced energy-optimization algorithms to reduce energy consumption, low-bias current technology, and a land-grid-array (LGA) footprint that guarantees excellent thermal, mechanical and electrical performance.

A very important feature of the two new modules is that they are 100 percent footprint compatible with the existing 12A BMR4613001 product. This means that customers will now have availability of these advanced POL regulators that offer three different output currents - 6 A, 12 A and 18 A - while only having to handle a single module footprint in new systems. This significantly simplifies board design and makes it easier for power architects to move to higher or lower current-handling power modules without needing to redesign the system board when upgrading to new microprocessors or other advanced logic devices such as FPGAs or ASICs.

The 18A (BMR4614001) power module should prove of particular interest to power designers as it is optimized to deliver 18 A at 1.8 V, making it ideal for processors operating at sub-2V core voltages. In fact, it is the first product of its kind to deliver this level of output current in a 12 x12 mm footprint, while also delivering automatic loop compensation and full PMBus command capability.

The Dynamic Loop Compensation integrated into the 6 A BMR4612001 and 18 A BMR4614001 is based on "state-space" or "model-predictive" control, which guarantees stability while also achieving the optimum dynamic performance without requiring any external components. The new products perform an automatic compensation routine based on measured parameters, which enables the construction of an internal mathematical model of the power supply including external components such as filtering and parasitic resistors. Based on the 'state-space' mathematical model rather than traditional proportional-integral-derivative (PID) regulation, the devices use closed-loop pole placement and a model based on the resonant frequency of the output filter, thereby reducing the number of output capacitors required for filtering and stability. This technology is highly suitable for FPGA and processor applications where low-ESR decoupling capacitors are used currently.

The DLC is designed to accommodate the vast majority of applications via PMBus commands. Board-power designers can therefore tailor the loop compensation; for example, in low-output voltages to enhance the recovery time at load release by enabling a negative duty-cycle using the LOOP_CONFIG PMBus command. Many other parameters can be simply adjusted and monitored without any hardware modifications.