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Synchronous rectification has become the standard for high-efficiency power converters. The perpetually decreasing supply voltages that are required by the applications make the voltage drop across a discrete rectifier intolerable. Most pulse-width modulated (PWM) integrated circuits do not provide an appropriate drive signal for synchronous rectifiers. The main switch signal can be used, but typically requires buffering because of the additional load.
Sometimes an extra winding on the transformer is used to drive the rectifier. In both cases, the timing of the signal can cause serious problems. If the timing of the main switch and rectifier are incorrect, drain-source body diodes may conduct, possibly resulting in current shoot through.
Little can be done about the timing of an extra transformer winding, and yet it is often used because of its simplicity. Higher performance can be obtained by using the main-switch signal coupled through a gate-drive transformer. The propagation delay is minimal until you add the required buffer. Often, this buffer is simply a pair of discrete transistors to minimize the delay. Sometimes a gate-drive IC is used.
The circuit in Fig. 1 demonstrates a simple alternative approach to minimizing delays and achieving adequate buffering. The circuit is a flyback converter, although the same method can be used with other topologies. In this circuit, a single FET driver is able to drive both the main switch and the synchronous rectifier. The circuit also helps tune out shoot through.
The drive to the main switch, Q1, is buffered at turn-off by Q2, and the synchronous rectifier, Q3, is buffered at turn-off by Q4. Thus, the apparent load is only one transistor. R1 slows the turn-on of Q1 to match the timing of the turn-off of Q3, making a high degree of timing flexibility possible.
When PNP transistors were substituted, the transitions could not be synchronized to the same degree. Q2 and Q4 are Si2301BDS p-channel MOSFETs from Vishay (Malvern, Pa.). They are rated for 2.4 A with a typical gate voltage of about 1.5 V. This keeps the voltage at the gate of Q1 low enough to prevent any unwanted conduction. On the rectifier side, the dc restore circuit uses low-voltage zeners to provide a negative bias and ensure full turn-off of Q3. Fig. 2 shows the resulting waveforms at input and output.