Novel SiC Diode Solves PFC Challenges
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Wide-input-range power factor correction (PFC) converters present some of the most difficult component challenges in ac-dc power electronics. With an operating input-voltage range that can extend from 265 Vac down to as low as 75 Vac, the range of operating conditions is relatively extreme — even more so considering the current operating range and duty-cycle demands. This places high stress on both diodes and MOSFETs. Even in a moderate-power 600-W converter, where maximum output power at brownout recovery is 750 W and average rectified output current from the boost converter is about 2.5 A, the peak input current for the ac waveform can be in the range of 16 A to 20 A. Furthermore, diode and switch ripple current will be 25% to 40% higher, depending on design parameters for the boost inductor.
To understand the design requirements for the boost rectifier, we'll analyze the operating conditions, including current, voltage and dV/dt encountered in the popular single-phase boost converter topology. This analysis will encompass low-line and startup conditions with marginal soft-start functionality. Then, we will examine how a new merged-structure device combining pn junction and Schottky operating modes in one diode meets these challenges while reducing component and system costs compared with earlier high-performance solutions.
The commonly used converter topology for moderate-power switched-mode power supplies (SMPS) is the single-phase boost converter (Fig. 1). When this converter is operating in continuous conduction mode (CCM) under moderate to full load, the current in the boost inductor is continuous. This configuration is more practical for higher power levels because the ripple current, which must be filtered by the EMI filter, is a much lower level than in the critical or discontinuous mode boost.
However, CCM presents other problems, because the boost rectifier must be commutated while carrying high forward current. The reverse recovered charge (QRR) causes the diode to look like a short to the boost MOSFET until the charge is cleared from the diode and voltage can rise across the diode. This is a large source of switching loss in the CCM PFC converter, and this loss is dependent also on the peak operating current and diode temperature for pn diodes.
Boost Diode Calculations
First, let's estimate the peak input current and RMS input current for the boost PFC stage based on the required output power (POUT) target efficiency (η) and the RMS input voltage ():
The chosen inductor value for a PFC converter is based on the duty cycle and on time relationships for the peak of the ac waveform at low line. The inductance is also based on the ripple-current level that can be tolerated, which is typically in the range of 20% to 30%. From the input-to-output duty cycle of the boost converter, VOUT/VIN = 1/(1-D), the duty cycle for 85 VacIN and 400-V bulk bus is derived:
From this, a working value is estimated for the boost inductor (LP):
With current design practices for high-density power supplies, this estimate will be the minimum inductor value at low line considering safe permeability droop for powdered-core inductors using materials like MPP, Kool Mu and other materials with a soft BH curve. This is reflected in the values shown in the table, which include full load at low-line inductance values as well as no-load values. The latter values reflect the expected inductance at higher line voltage and lower inductor current.
To calculate the current operating conditions for the boost diode in detail, we'll have to consider the high-frequency switching behavior with the boost inductor, as well as the low-frequency ac mains waveform. To address this, the operating ripple current and pulse-by-pulse operation is calculated using MathCAD. The input voltage and current determine the operating points for the boost diode over one complete ac cycle at the specified input voltage — low line in this case.
First, functions specifying the ac operating period and the input voltage, as well as an indexed variable for the period, are defined:
Using the previously calculated values for RMS input current, a waveform for the PFC input current can be calculated:
Next, the duty cycle for boost switch and diode will be calculated over one ac mains period, as the prelude to calculating the ripple current. First, the switch duty cycle (dS) is defined:
where DSMAX is the maximum duty-cycle capability of the PFC controller. The diode duty cycle (dD) takes the remainder of the clock period:
Next, the ripple current ΔI as a function of input voltage and duty cycle is calculated for the switch and diode:
The minimum and maximum diode currents due to ripple current in the inductor can be calculated over the mains period, starting with the maximum diode current (IDMAX):
This assumes one diode in the boost rectifier position; otherwise, the diode current is shared between the diodes. The shared current technique is generally only feasible with Schottky diodes because of their positive coefficient of on-state voltage with temperature.
The RMS current for the diode () is calculated by integration. This gives a different, perhaps even misleading, picture of the diode load as can be seen in the table.
The table shows the calculated PFC output power and other parameters for SMPS at selected output power levels between 350 W and 1000 W. The recommended full-load and no-load inductor values are shown for two operating frequency ranges, 100 kHz and 250 kHz, and the RMS and peak currents with 85-Vac input line voltage have been calculated. This is representative of typical worst-case steady-state low-line conditions. Actual worst-case conditions can be more extreme under dynamic conditions, such as startup or brownout recovery, and when the bulk bus voltage has sagged lower than the nominal 300 V due to cycle skip or high load. These factors can increase the current level 20% to 25%.
At first look, this seems to present primarily a forward-current problem, but consider that, for conventional pn diodes, the diode-induced switching loss from QRR is strongly dependent on junction temperature and operating current. Consequently, a low duty cycle/high peak current is a worst-case situation that dramatically raises the stress on the boost switch and the diode from the QRR-induced switching losses when operating at low line. The difference in QRR is a function of operating current, temperature and the rate of di/dt. So with silicon pn diodes, the upper switching frequency limit will rarely be much higher than 100 kHz in order to avoid thermal runaway.
Fig. 2 details the calculated current waveforms for steady-state low line. These are representative values for a 1-kW PFC converter with 110-W output power, and the suggested boost inductor for 100 kHz. The green trace is the input current for 85-Vac line voltage, the blue trace is the calculated average switch current and the red trace is the calculated average diode current. Note that the yellow trace shows the peak diode current level when the boost switch turns off and the boost rectifier begins conducting.
It is possible to avoid QRR-related switching losses in PFC converters by using 600-V silicon carbide (SiC) Schottky diodes, which have become commercially available since about the year 2000.[1] With no hole-carrier-related QRR, and only capacitive displacement current as a switching loss factor, exceptional high-speed switching performance has been demonstrated by commercially available components.[2, 3, 4]
However, like their silicon Schottky counterparts, the SiC Schottkys use only majority carriers, and the positive temperature coefficient of on-state voltage limits their surge-current capability. In applications like wide-input-range PFC converters, the overcurrent limitation may dictate that the component be sized more for this characteristic than the nominal operating conditions.[5, 6] How much of a problem can this be in a typical application, considering the dynamic events usually define the boundary conditions?
Surge Current at Startup
Fig. 3 shows the diode current waveform in an SDT06S60 600-V SiC Schottky diode in a commercial power supply for which the controller IC doesn't have a particularly well-managed soft-start characteristic. The peak startup current in the boost diode exceeds 30 A for portions of the startup period. This test was conducted with an ambient temperature of 25°C, and measured from a cold starting condition.
In Fig. 4, the same event is displayed with a higher main sweep speed of 2 ms/div, and an expanded sweep on the B channel of 5 µs/div. In this view, it's clear that the peak diode current is about 32 A with an operating duty cycle of about 33% (4 µs out of the pulse period of 12 µs). The question that arises when this behavior is discovered during the testing of a new design is, is this safe and, if so, with what margin?
One way to estimate the margin is to use a wideband long-channel-length scope with integration capabilities and establish the I2T stress on the diode. If an instrument like this isn't available, another possibility is to prepare simulations using full electrothermal SPICE or SABER models. Note that conventional SPICE or PSPICE models lacking transient thermal impedance structures and the modification of device parameters as a function of junction temperature will not be usable evaluating this type of problem.
In this case, an analysis was performed using the current load waveforms as the input to the SiC Schottky rectifier. Due to the positive temperature coefficient of forward voltage, the actual power dissipation and predicted junction rise are variable, depending on starting junction temperature. At 25°C, the typical ΔT is ~35°C and the worst-case part is ~52°C, posing no problem.
But with increasing ambient temperature, the situation changes. At a TCASE starting temperature of 75°C, the typical ΔT is ~42°C and worst case is ~63°C, possibly resulting in a terminal junction temperature of ~138°C, which is still in spec but does not meet the derating criteria of many SMPS customers in the computing segment. If we consider the case of the 125°C starting temperature — which one would hope is outside the realm of likelihood — a typical ΔT of ~50°C results, with a worst-case rise of ~75°C. This places the junction temperature at ~200°C, well outside the safe specification for the package and die attach.
Although SiC is fu an 8-A or 10-A rating to meet the surge. The required oversizing for surge current in wide-input-range PFC applications is part of the perception of a poor value proposition for SiC Schottky diodes in general.
Merged-Structure SiC Diode
To address this problem optimally, a new concept for the high-voltage SiC rectifier has been developed using a merged-structure device combining both Schottky and pn structures, with a low-ohmic connection of p regions to the anode of the device (Fig. 5).[7] This concept takes advantage of the wide bandgap potential of SiC, where under normal operating conditions, the high pn junction potential (~3 V to ~4 V) of SiC will prevent conduction of the pn structure. Only in overload conditions will this forward voltage be reached, and the pn structure will provide hole-carrier injection for conductivity modulation of the drift region.
The p regions, sometimes employed in floating p bodies in Schottky devices, have other benefits in that they will concentrate the maximum electrical field away from the Schottky barrier surface. This allows using a higher-maximum field potential in the blocking mode without degrading the barrier and compensates for the area used by the P wells. This also provides a true and consistent avalanche breakdown characteristic — which is not possible across a Schottky barrier — that secures additional ruggedness in the handling and testing. Due to the material characteristics of the SiC crystal lattice and the very thin epi layer possible with SiC high-breakdown field strength, the impact of pn junction operation on the normally negligible stored charge of the SiC Schottky diode is essentially unmeasurable, even at 10 times the rated current.
The combination of transfer functions of both Schottky and pn structures depicted in the graph of Fig. 6 is typical of a 4-A diode. The Schottky transfer function shows a junction potential around 0.8 V with an initial linear resistance that saturates with increasing current due to current density, ultimately resulting in a rapidly rising forward voltage when the current destruction point of the diode is reached. This saturation current is not fixed but rather a function of junction temperature; with increasing junction temperature, the maximum current is reduced, which results in lower surge capability.
Contrast this with the pn junction curve: the initial junction potential is quite high due to the wide bandgap of silicon carbide, but due to hole-carrier injection, the achievable current density is much higher — following a very linear function that actually extends up to 100 times the diode rated current, as testing has shown. In principle, combining these structures should result in the lower forward dissipation of the Schottky at current levels up to a few times the rated forward current of the diode, with the large overload capability and higher peak current of the pn structure.
In practice this is the case, as the current saturation effect of the Schottky is removed (Fig. 7) and the 400 µs pulse operating range is extended to beyond 10 times the rated current over a range of starting junction temperature of 25°C to 175°C.
Returning to the startup surge current problem, let's look at a similar example for a PFC using the 4-A diodes (Fig. 8). As previously, we use the measured current waveform as an input for simulation of the junction temperature rise of the diode. This graph compares the predicted junction temperature rise between the original 4-A devices and the merged-structure diode, based on a starting temperature typical for steady-state operating conditions. This simulation is representative of what occurs in many cases when there is a brief power interruption, perhaps just a few cycles, and a restart occurs when the equipment is hot. The advantage is quite clear toward the end of the startup phase, with a better than 2-to-1 ratio in predicted junction temperatures. The peak junction temperature is well within preferred derating criteria as well as nominal device limits.
In practice, with this merged-structure technology, a diode of typically one-third lower current rating can be used with safety and performance similar to the more expensive higher-current-rated conventional SiC Schottky diode. This comes with no loss in overall performance and significant secondary benefits, including consistent avalanche breakdown capability and demonstrated safety with high dV/dt.[7]
References
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Rupp, R.; Treu, M.; Mauder, A.; Griebl, E.; Werner, W.; Bartsch, W.; and Stephani, D. “Performance and Reliability Issues of SiC-Schottky Diodes,” presented at International Conference on SiC and Reliability Comp, 1999.
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Kapels, H.; Rupp, R.; Lorenz, L.; and Zverev, I. “SiC Schottky Diodes: A Milestone in Hard Switching Applications,” proceedings from PCIM 2001.
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Agarwal, A.; Singh, R.; Ryu, S.H.; Richmond, J.; Capell, C.; Schwab, S.; Moore, B.; Palmour, J. “600V, 1-40A Schottky Diodes in SiC and Their Applications,” proceedings from International Power Electronics Technology 2002 Conference, pp. 631-639.
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Rupp, R., and Hancock, J. “SiC Power Devices Tailored for Power Management and Supply Applications,” CD-ROM proceedings from CPES-NSF Silicon Carbide Symposium, May 2003.
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Zverev, I. “Switching Frequency Related Trade-offs in a Hard Switching CCM PFC Boost Converter,” CD-ROM proceedings from APEC 2003.
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Zverev, I.; Kapels, H.; Rupp, R.; and Herfurth, M. “Silicon Carbide Schottky: Novel Devices Require Novel Design Rules,” proceedings from PCIM 2002.
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Bjoerk, F.; Hancock, J.; Treu, M.; Rupp, R.; and Reimann, T. “2nd Generation 600V SiC Schottky Diodes Use Merged PN/Schottky Structure for Surge Overload Protection,” proceedings from APEC 2006.