Workshop coverage extends from software to ATE gesture interfaces

Test Vision 2020 will cover a range of topics, from a voice/gesture ATE interface to the role of software, according to Ajay Khoche, general chair, and Pete Hodakievic, program chair. The workshop will take place July 10-11 in San Francisco in conjunction with Semicon West.

In a phone interview, Khoche and Hodakievic previewed this year's event. Khoche noted this year marks the sixth iteration, adding “We have established ourselves as valuable platform for people to contribute and speculate about the future.” He noted that over the years the workshop has attracted a nice mix of executives, test managers, applications engineers, and ATE vendor representatives, and he expects that to continue this year.

The event, which commences 3 p.m. Wednesday, includes a keynote, an invited speaker presentation, two panel discussions, and papers organized into four session. “Our program originally had spots eight papers; we received 16 and accepted nine,” said Hodakievic.

Erik H. Volkerink, chief technology officer at Flextronics, will deliver the Wednesday afternoon keynote, titled “Product Foundry: Next Paradigm in Product Design and Engineering.” Khoche said Volkerink, formerly with Advantest and Verigy, will discuss how electronics manufacturing services (EMS) companies like Flextronics will have to adapt in terms of creating new products at the system level and how to assemble and test the products sufficiently to deliver the quality the customer is expecting. Khoche added that Volkerink will probably touch on time to market: “How do you incorporate a test strategy across many different suppliers in your supply chain to improve time to market, time to volume, and time to yield?”

How Much Test is Enough?

Wednesday will continue with the first panel discussion, “How Much Test is Enough Test?” Panelists will include Volkerink, Ira Feldman of Feldman Engineering, Scott Gulas of Texas Instruments, Gary Fleeman of Advantest, and Steve Ledsinger of Broadcom. Greg Smith of Teradyne will serve as moderator.

This panel, Hodakievic said, originated in discussions of new types of faults that can occur. He cited an MPU example: “If product uses too much power—is that a fault, and will you throw it out? We've got a whole bunch of faults that can manifest themselves. They might not cause system failure, but they do result in unoptimized performance. Do we throw those away?” He noted that as SoC complexity increases, test engineers have to make decisions about what to test and what kind of faults are important. “You can't screen for everything. There's more logic on these chips, and your test budgets are not increasing. If anything they are decreasing. You've got to make tradeoffs somewhere, and this panel will discuss how you make those tradeoffs.”

Time to Market and Product Cost

Session 1 will begin Thursday morning at 8 a.m. with the title “Faster Time to Market with Lower Product Cost?” Time to market and low product costs are the ultimate goals, Hodakievic said. As an approach to achieving those goals, James Quinn of Multitest will present a paper titled “Minimizing Cost of Calibration and Test (COCT) to drive cost reduction of MEMS” and Dan Glotter of Optimal Test will present “Escape Prevention and RMA Management.” Glotter, said Hodakievic, will discuss data across numerous customers, highlighting what's common to see what changes could be made to reduce costs and speed time to market.

Concluding the session will be a paper titled “Cell-Aware-Test, a Must-Have for Leading Technology Nodes,” by M. Keim, F. Hapke, W. Redemund, A. Glowatz, and J. Rajski of Mentor Graphics and M. Reese, J. Rivers, A. Over, V. Ravikumar, and J. Rearick of AMD. The cell-aware test the topic should be a good one for the workshop audience, Hodakievic said, adding that the introduction of new fault models was in line with conference goals.

Game Changers

Session 2 is titled “Test program game changers?” Tony Lendino of Texas Instruments will present “Automatic Test Program Generation of Analog Trim,” and Patrick Conreaux of AMD will present “New Approaches in ATE Binning.”

ATE providers typically give customers a set of templates and usage models, Hodakievic said, and for most companies that is sufficient. “However,” he added, “there are trail-blazing companies that have really rethought how to increase test flexibility and reduce defects. These companies have adopted integrated software engineering principles into test-program design, and they have been able to achieve what I think are revolutionary changes.”

Hodakievic said he has first-hand experience with the work AMD has done, but the work that TI has done is very similar—it just applies test standardization to analog. “For the last couple of years AMD has presented on test standardization in the digital realm, and extending it into analog makes a lot of sense,” he said.

With respect to AMD's paper on binning, Hodakievic said, it’s a follow-up to the last two presentations with extensions to adjusting binning on the fly without the tester to re-bin parts offline, which can lead to improving overall equipment effectiveness (OEE). OEE can be a difficult topic to discuss without giving away too much data, he said, but added the binning paper may segue into that subject nicely. “I am hoping from a discussion standpoint we can not only talk about the software aspects but the OEE aspects that this paper enables,” he said.

Invited Address: LED Lighting

Thursday morning will conclude with an invited speaker address. Sri Jandhyala, strategic marketing director, Lighting Segment, ON Semiconductor, will present “LED Lighting—Opportunity, Challenges, and the Future.” Hodakievic said this topic arose out of the awareness that “…green energy, green power, the whole green movement has taken hold. Solar is the next big thing at Semicon West, and we wanted to tap into that. More companies are getting involved. LED lighting is a nice bridge.”

Khoche added, “Traditionally, we have used the invited speaker's slot to look at a new emerging technology. Last year we looked at MEMS. So we were looking for a topic that is not so much the mainstream yet but is bound to become mainstream.”

High-Speed Test

Thursday afternoon will begin with a session on economical high-speed test. Mark Roos will present a paper titled “True HVM RF Testing Beyond 20 GHz,” and Al Crouch of ASSET-InterTech and Khoche will present “Leveraging Functional FPGAs for Board and System Test.”

Speaking of his and Crouch's paper, Khoche described a paradigm shift. Traditionally, board test has employed a bed of nails. Subsequently, boundary scan has been added. “Now,” said Khoche, “we are at the stage where some of the chips, like DDR3 and DDR4 and onwards, cannot be tested using just boundary scan,” which cannot meet the frequency and performance demands. The method Crouch and Khoche propose is to use the FPGAs that are part of the application for test. You are not inserting a new FPGA on the board but rather reprogramming an existing one for test purpose so that chips connected to the FPGA can be tested in a functional mode at speed. “You can achieve high speed and better quality for the board without having to insert new logic—you just reuse what you already have,” Khoche explained. He said the emerging IEEE 1687 standard is enabling the creation of embedded testers.

Is This the Future?

The final paper session is titled “Is This the Future?” Roy Chorev of Teradyne will present “Will the next generation of test engineers be all software engineers?” And Keith Schuab, Hui Yu, and Minh Diep of Advantest will present “Xbox Speech Recognition Virtual Engineering Assistant: Vision for Future: Software Interface for SoC Test Systems.”

Commenting Chorev's paper, Hodakievic said, “When Roy submitted it, it struck a chord with me personally because I am a software guy who happens to have a career in test. And part of the work we did that I personally led at AMD and that other people are getting onboard with is really extending software principles into the realm of test.”

He added, “My personal experience is, let the software engineers write the test programs, and let the hardware guys focus on the hardware and use the test program to get their answers. Let those guys be the requirements generators. We'll see what Roy has to add, and I am hoping his presentation opens up the conversation.”

Hodakievic said the main focus of previous workshops has been hardware, with software discussed on the margins. “I'm hoping this conversation is yet another way to bring together the software and hardware folks—getting them talking in the same language that is different from either the software or hardware language.”

Hodakievic next commented on the Xbox Kinect paper: “What Advantest is exploring is the question, 'What would it be like if we could use body gestures and voice commends to interact with the tester?' The ultimate solution may not necessarily be an Xbox, but the Xbox is a means to an end—it's something available now to prototype with. It's readily available, so if you wanted to try it, you can go get some Kinects and connect them up.” Added Khoche, “This could be a revolution in the industry in terms of human-machine interaction and how it applies to test.”

Time Capsule

The workshop will conclude with a panel discussion titled “The Next Big Innovation in Test.” Participants include Abhijit Chatterjee of Georgia Tech University, Bill Bottoms of 3MTS, Mohamed Hafed of Introspect Technology, Steve Wigley of LTX-Credence, and Octavio Martinez of Qualcomm. Roger Barth of Micron will serve as moderator.

Hodakievic described this panel as a time capsule: “The whole idea is to look forward ten years from now and figure out what change or inflection is going to have the biggest impact on semiconductor test. Then somewhere between five and ten years down the road we can have another panel and play back what predictions we made back in 2013 and see how many of those have come true. Has the industry proceeded the way we thought it would, or is it drastically different, and if so in what ways?”

He continued, “We've assembled some forward-looking people, and we going to ask them to make their predictions. We will capture it all. We will archive the slides and video of the panel. Down the road, we will put together a montage that we will integrate into another panel and see if we have any Bill Gates' '640k is all you'll ever need' kind of moments or if we are better than that.”

Khoche concluded by noting that the IEEE Instrumentation & Measurement Society is serving as this year's technical sponsor. Corporate sponsors include Advantest and Teradyne (platinum sponsors); FormFactor Microprobe, Solidus Technologies, and Mentor Graphics (gold sponsors); and LTX-Credence, Synopsys, inTEST, and Roos Instruments (silver sponsors). EE-Evaluation Engineering is serving as press partner; other partners include Semicon West, the IEEE Test Technology Technical Council, and GSA.

Early registration ends June 7. Visit the registration page for more information.

See these related articles:

“Test Vision 2020 and the IEEE TTTC Issue Call for Best ATE Paper“—An award selection committee is now accepting recommendations for a paper published in 2012 that contributed to the advancement of the ATE field.
“Cascade's Ahlgren Offers Clear View of Semiconductor Test“—In an exclusive interview, Deb Ahlgren, vice president of marketing at Cascade Microtech and the vice general chair of the Test Vision 2020 Workshop, discusses test in general and the workshop in particular.
“Big Data Comes to Semiconductor Test“—Tom Morrow, vice president, SEMI, comments that big data and test will be principal discussion points on the Semicon West show floor and during conference sessions.
“Test Vision 2020 to Address Test Strategies, Technologies, and Applications“—SEMI announces Test Vision 2020 details.

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