Boundary-scan derivatives reach the Internet of Things

JEDOS offers a range of functions for test, validation, and calibration as well as programming. It supports calibration functions for a DDR RAM controller to verify access security or to get optimized initialization parameters through appropriate margin tests.

Thanks to its functionality, JEDOS shifts more test execution even further into the target, making for an important step on the way to embedded ATE. In a video presentation, Thomas Wenzel, managing director of GOEPEL electronic and CTO of the JTAG/boundary scan division, commented, “Due to JEDOS, the balance between external test and internal test is shifted more into the target.”

The advantages provided by JEDOS enable comprehensive real-time test of IoT devices without using native firmware, Wenzel said, thereby enabling software developers to take advantage of preverified prototype hardware and obtain more efficient fault isolation.

The rapidly increasing complexity of IoT devices also creates new demands on the performance of the tools used both in design validation and in production test, said Wenzel, adding that the demands are met through the in-the-target embedded JEDOS solution.

Wenzel explained that with the JEDOS strategy, the operating system is loaded via JTAG, and it transforms the native microprocessor into an embedded processor for test. For example, he said, the processor can execute real-time functional tests and diagnostics, and it also can program different devices. The strategy, he said, allows for efficient isolation of hardware and software faults and supports validation, calibration, debugging, and programming.

JEDOS is the first result of the previously announced cooperative effort with KOZIO. The partnership aims at the development of innovative embedded tools in several stages.

Processor IP and debugging

Also in May, ASSET InterTech debuted an eBook that describes how trace debugging takes advantage of IP in processors to help software engineers track back to the root cause of a code bug and fix it.

“The value of trace has moved to a whole new level with the recent announcements concerning Intel Processor Trace. For quite some time now, ARM has provided a variety of trace macrocells,” said Larry Osborn, product manager at ASSET and author of Hardware-Assisted Debug and Trace within the Silicon, in a press release. “This IP in the silicon gives software engineers trace capabilities that are much more powerful than legacy trace methods. The bottom line is that bugs in complex code can be found a lot faster now with tools for hardware-assisted trace.”

The new eBook discusses how trace debugging can shorten a new system’s time-to-market.

Traditional boundary-scan advances

Companies also are working to evolve their more traditional boundary-scan offerings for PCB and assembly test. For example, in April GOEPEL said it is augmenting its SCANFLEX JTAG/boundary-scan hardware platform with the SFX-5296LX, a next-generation mixed-signal I/O module, which makes even nonscannable partitions testable through boundary scan. It can test an assembly with just one boundary-scan IC.

The SFX-5296LX is equipped with diverse dynamic test resources for each channel, such as a frequency counter, an event detector, an arbitrary waveform generator, and a digitizer. It includes a total of 96 single-ended channels and extends boundary-scan test to nonscannable components such as connectors, clusters, or analog interfaces. To increase flexibility, each channel can be configured as input, output, and three-state and can be easily programmed using many available parameters. These include switchable pull up/pull down or selectable slope steepness for the driver.

The new SFX-5296LX uses the parallel I/O bus and therefore enables much faster data transfer than with serial, via TAP-driven I/O modules. Based on the test resources available per channel, both static and dynamic at-speed tests are feasible, allowing a significant improvement of the structural fault coverage along with more flexible test strategies. By this means, only one SFX slot is needed. To increase the number of channels, several modules can be operated simultaneously.

And at the SMT/Hybrid/Packaging show in Nuremberg in May, GOEPEL presented the JULIET Series2, the company’s latest generation boundary-scan production test platform. The compact desktop system includes fully integrated boundary-scan test hardware, a power supply, and an interchangeable adapter system for flexible UUT contact. The new JULIET (derived from JTAG Unlimited Tester) is particularly applicable for production testing in the low- and mid-volume range as well as for repair.

For its part, Keysight Technologies recently announced that its Keysight x1149 boundary scan analyzer will expand its coverage capabilities to test the Intel microarchitecture codenamed Skylake.

The Keysight x1149 analyzer is designed to maximize structural test coverage for board designs that incorporate Intel processors. The new test application will help electronics designers and manufacturers use the x1149 to test boards with the new microprocessor architecture using boundary scan and Intel Silicon View Technology (Intel SVT).

Boundary scan complements functional test

And in a recent article, Peter van den Eijnden, managing director of JTAG Technologies, told Jos Cortenraad of Dutch High Tech2 that PCBs often are subjected to go, no-go functional tests. But should functional test fail, a boundary-scan system such as JTAG’s JT 5705 mixed-signal boundary-scan tester can detect whether the problem is an open solder joint, a short, an incorrect component, or a faulty component—as long as the board has been designed for manufacturability.

The JT 5705 was presented at the APEX Expo in February. At the time of the product’s release, van den Eijnden said, “We received extensive market feedback on how the next generation of JTAG/boundary-scan testers should look, and increasingly we have been asked to provide analog stimulus and measurements alongside more traditional digital I/O systems. The new JT 5705 provides all this and more in a really convenient and low-cost package.”

References

1. Nelson, R., “Boundary scan pioneers go deep,” EE-Evaluation Engineering, May 2015, p. 18.
2. Cortenraad, J., “Progress in testing PCBs,” Dutch High Tech, April 2015, p. 28.

For more information
ASSET InterTech
GOEPEL electronic
JTAG Technologies
Keysight Technologies