Measuring digital clock stability and jitter with an oscilloscope

Clocks are the heartbeats of embedded systems, providing timing references and synchronization between components, subsystems, and entire systems. Incorrect clock signal amplitudes and timing can impact reliable digital circuit operation. Noise and timing aberrations or jitter on clock signals can cause degraded or intermittent system performance. This means that thorough characterization of clock signals is a critical step to ensuring reliable embedded system designs.

Fundamentally, jitter is any unwanted deviation in signal edge timing from where it should be. Some jitter is inevitable in any system and small amounts won’t have much impact on system performance. But embedded systems must be able to survive outside of a controlled lab environment and small problems can easily become big problems under the right (or wrong as the case may be) conditions. As such, for systems to operate reliably under a broad range of conditions, thorough characterization of digital clock stability levels and jitter is a must.

Figure 1. Measuring amplitude: the low level of the clock in this example is about 750 mV and the high level is about 2.4 V.

Amplitude measurements

Visual inspection of a signal’s amplitude is the place to start when evaluating clock signals. As shown in Figure 1, the horizontal and vertical labels inside the graticule let you determine that the low level of the clock in this example is about 750 mV and the high level is about 2.4 V. The clock period is about 25 ns, which corresponds to 40 MHz. For some quick debug tasks, this measurement precision may be sufficient.

More precise amplitude and timing measurements are made by zooming in on one cycle of the signal and using cursors. Even though measurement resolution can be significantly improved using this approach, the measurements are based on a single cycle of the waveform and can be difficult to make if the signal is varying over time.

Another way to gain more insight is to use automated measurement algorithms that use digital signal processing on the digitized waveforms. Figure 2 shows how these algorithms work. Notice that the Top and Base measurements are similar to the ones previously made with the horizontal bar cursors, but with higher resolution. Additionally, the Peak-to-Peak measurement is equal to the difference between the Maximum and Minimum measurements, and the Amplitude measurement is equal to the difference between the Top and Base measurements. These readings provide a good snapshot, but how are the measurement values varying over time?

Figure 2. Automated measurements use digital signal processing on digitized waveforms.

One way to see how results vary over time is with a results table that displays measurement values and measurement statistics. Measurement statistics over all acquisitions are calculated from the time the first acquisition is started through the current acquisition. This is useful for gaining insight into stability over longer time periods. Based on the accumulated statistics of the amplitude measurements, you can compare the measurement values to the data sheets of the clock driver and the components being driven by the clock signal to verify that amplitude characteristics are within specifications. Some examples include ensuring that:

The Max value of the Maximum measurement and the Min value of the Minimum measurement are within the receiver’s absolute input voltage range spec
The Min value of the Top measurement is greater than the driver’s VOHmin and the receiver’s VIHmin spec
The Max value of the Base measurement is less than the driver’s VOLmax and the receiver’s VILmax spec

Frequency Stability Measurements

Similarly, automatic timing measurements can be used to provide quick horizontal measurements. The μ’ values shown in the measurement results on the right side of the display in Figure 3 represent the mean timing measurement values for the current acquisition. In this example, the Period measurement provides similar results to the measurement made with the V Bars cursors discussed earlier, but with higher resolution and faster updates.

Figure 3. Stability can be determined with automated period measurements.

As expected, the Period measurement is equal to the sum of the Positive Pulse Width and Negative Pulse Width measurements, and the Frequency measurement is the reciprocal of the Period measurement. From here, you can compare the measurements to the component data sheets of the receiver components that are driven by the clock signal to verify that the timing characteristics are within the specifications. These can include:

Confirming that Max and Min values of the Frequency measurement are within the specified clock frequency (fclock) range
Verifying that the Min value of the Positive Pulse Width measurement is greater than the minimum pulse duration spec tw (CLK high)
Validating that the Min value of the Negative Pulse Width measurement is greater than the minimum pulse duration spec tw (CLK low)

Standard automated timing measurements provide a good starting point for jitter analysis, by verifying that the clock frequency is meeting specifications. Adding measurement statistics, such as minimum and maximum frequency, provides confidence that the clock pulses are continuous. And standard deviation (σ) provides a quantitative measure of the frequency stability over time. However, these statistics give little insight into the manner of frequency variation.

For more insight, the acquisition time window can be increased to increase the number of cycles in the acquisition and thus the number of available cycle measurements. Using a time-correlated Time Trend display you can then observe the variation of frequency measurements across the acquisition. A time trend display provides a better understanding of the frequency variation than measurement statistics, but it is still difficult to determine if the variations are random or caused by systematic factors such as other nearby signals.

More clues

The histogram of the frequency measurement values, in the upper left corner in Figure 4 suggests that the variations in the frequency are not completely random (not a classic Gaussian or bell curve). The shape would suggest that there may be other signals cross-talking into the clock signal. The spectrum plot shows significant frequency components at about 7 MHz and 20 MHz. These measurements and knowledge of the rest of the design may be helpful in determining the root cause of the clock frequency variations, but it is difficult to know which of several potential causes is dominant. For that, you need to decompose the timing jitter into its components.

The place to start when looking for jitter is Time Interval Error (TIE) and phase noise measurements. TIE quantifies the time variation of a clock signal from an ideal signal. Jitter analysis applications offer a quick analysis of the 40 MHz clock signal, shown above, including TIE analysis and an eye diagram. This is accomplished by comparing automated measurements of TIE with an ideal signal. You gain deeper insight through the decomposition of timing jitter into Total Jitter (TJ), Random Jitter (RJ), Deterministic Jitter (DJ), Periodic Jitter (PJ), Data-Dependent Jitter (DDJ), and Duty Cycle Distortion (DCD).

Figure 4. The variations in frequency may not be completely random, indicating the presence of jitter.

In our example, as predicted from the histogram of the frequency measurements shown in Figure 4, there is a systematic distortion of the clock. The deterministic jitter is much higher than random jitter, and the deterministic jitter is dominated by duty cycle distortion. We were able to observe significant jitter components at 7.1 MHz, 20 MHz, and 30.3 MHz. In this case, a nearby 7.1 MHz clock proved to be the aggressor, interfering with the 40 MHz clock signal.

In this example, we also looked at this same circuit on a different prototype board. In doing so, we noticed an occasional circuit malfunction. However, there wasn’t any obvious problem when viewing the clock signal on the display. One method to gain more insight is to use an acquisition mode that can quickly capture millions of the 40 MHz clock signals and overlay them on the display. In this mode it can be seen in Figure 5 that there are some significant frequency variations on the clock signal on this board, which proved to be defect. As the display is “temperature-graded,” the wide frequency variations are shown in blue, indicating that they are relatively rare.

Figure 5. The wide frequency variations are shown in blue, indicating that they are relatively rare.

Now that we know these variations are there, we can plot the frequency measurements on a histogram with a logarithmic Y-axis to better understand the variations. Note that the logarithmic scale lets you see more detail at the low end of the scale. After allowing over 10 million frequency measurements to accumulate, the truly infrequent nature of the frequency variation appeared. The average frequency was very accurate, but occasionally drifted as low as 35 MHz and as high as almost 55 MHz. Without such statistical measurement techniques, infrequent anomalies such as these could go undetected.

With the knowledge that the frequency occasionally decreases, we used pulse width triggering to capture abnormally wide pulses along with the errors. In this case, we set the scope to trigger on a pulse width greater than 14 ns, which is more than the nominal 12.5 ns. The resulting frequency trend graph showed clearly that there were frequency excursions above and below the 40 MHz ideal.

Further analysis of this clock circuit showed that the phase-locked loop controller was occasionally being reset. When this happened, the voltage-controlled oscillator circuit lost lock and momentarily shifted from the proper frequency.

As the heartbeat of embedded systems, clocks are critical to maintaining timing references and synchronization across components, subsystems and entire systems. As these examples of measurements have shown, modern oscilloscopes offer a broad set of measurements that take the mystery out of characterizing and verifying jitter in clock circuits. EE