Hierarchical Processors Target Wearable Tech

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Developers delivering a single product have it easy. Pick a system-on-chip (SoC) microcontroller that meets the application requirements, and refine the software until it works as desired. The design task becomes more complex if more than one product is in the mix, especially if the requirements become more demanding. The typical approach is to have a single-core solution across the board with more powerful processors covering the high end.

These days, a 32-bit processor family can provide code compatibility from the low end to the high end. The low end tends to have lower power requirements but with lower performance. The high end has more performance, but power requirements tend to be significantly higher. Nimble programming can exercise run modes to reduce the amount of power used, though it is still a challenge to hit the low end of the spectrum.

An alternative approach is to incorporate multiple processing cores, usually two. One is a small, low-power core. The other is a larger, more powerful core. Minimal power is used when the larger core is shut down and the low-power core is used alone.

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Four-Stage Product Hierarchy

The Ineda Systems Dhanush Wearable Processing Unit (WPU) family spans four upward-compatible platforms based on Imagination Technologies’ MIPS processors (Fig. 1). The smallest, the Nano WPU, is a single-core system based on the MIPS microAptiv UC core (see “MIPS Aptiv Family Brings Consolidation And Raises Performance Bar” at electronicdesign.com). Designed for an always-on operation typical of the target platform, wearable devices, this low-power microcontroller can easily operate as an intelligent sensor hub. It includes the usual peripheral complement and on-chip SRAM.

The Nano is the lone single-core chip in the family. All the other chips are multicore solutions that are built symmetrically. The shared memory and peripherals are equally accessible by each core. The Micro dual-core solution adds a higher-performance microAptiv UP core. Like the Nano, it can run with just the microAptiv UC core using minimal power. The Nano is designed to run for a month on batteries. The other chips in the family should do as well if they are only using the low-end core and on-chip SRAM.

The Optima is essentially the Micro chip with a DRAM controller added. It targets applications that require more memory. By moving off-chip, significantly more storage can be included. The system can run with just the microAptiv UC core using on-chip SRAM to significantly reduce power requirements. This would be handy for delivering sensor hub support without turning on DRAM or the other core.

Finally, there is the Advanced chip (Fig. 2). This triple-core solution simply adds the interAptiv dual core. The programmer must determine which core will run or if all three can provide the best platform for an application. Of course, two of the three may work at some point. This hierarchical approach provides developers with more control over power utilization and performance. The compatibility between cores means programmers do not have to jump through different hoops depending upon which collection of cores is utilized.

As with most microcontroller vendors, Ineda will have a collection of SKUs with different peripheral, memory, and core complements. This includes pulse-width modulation (PWM) timers, analog-to-digital converters (ADCs), and communication ports. Moving up the chain will include more compute performance as well as more memory and peripherals such as hardware accelerators. The display controller on the Advanced will have PowerVR 3D graphics acceleration along with video decode and encode accelerators.

It is possible to take the family to even higher-performance solutions. Ineda Systems has yet to tap Imagination Systems’ high-end proAptiv core. This may take a while as Ineda must deliver and support the current family of chips. The company has a good start, including the SHASTRA software development kit (SDK) and reference platforms. The software includes a unified development environment and power profiling tools.

Wearable technology requires a mix of sensors and low-power operation. The WPU family looks to be an ideal platform to meet those needs, including scaling to devices that have more sophisticated display and input requirements.

Discuss this Blog Entry 2

on Jun 14, 2014

Ah, an application where power saving is done via a PMIC.
I wonder why only the 2-core versions (Optima and Micro) have DRAM while the 1-core version (Nano) doesn't.
If we were really after power saving, wouldn't we want to use static ram all the way instead of using a dynamic ram which consumes power (neglecting speed issues). Pardon me for my conflicted thoughts, I'm new to the semicon. industry and my foundation on monolithic electronics technology is still shaky. Very good article as always by the way. :)

on Jul 2, 2014

SRAM is expensive and external DRAM provides designers with more flexibility. What this family does is allow a programmer to run with the SRAM and the small core and shut down the DRAM and larger core when it is not needed. For example, a mobile device might acquire information via sensors and store it. This can be done by the smaller, more power efficient core. The user interface would run when someone pressed a button and then the other core and DRAM would be used.

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Bill Wong covers Digital, Embedded, Systems and Software topics at Electronic Design. He writes a number of columns, including Lab Bench and alt.embedded, plus Bill's Workbench hands-on column....
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