MIPS Aptiv Family Brings Consolidation And Raises Performance Bar
Like most processor vendors, MIPS Technologies is moving to a new naming convention to provide a better branding of their their next generation architectures. The entire product line is called Aptiv. The product line is divided into three families (Fig. 1): the high end proAptiv, the midragne interAptiv and the microcontroller microAptiv.
The new product line brings new designs across the board. The older architectures like the M14K Series microcontrollers to the multicore 1074K Series will still be available but new designs will employ the new families. There will likely be additional partitioning of these new families in the future depending upon design requirements.
Figure 1. The Aptiv family spans three different architectures: proAptiv, interAptiv, and microAptiv.
The new flagship is the proAtiv family that supports from one to six cores (Fig. 2) delivering 4.4 CoreMark/MHz. It is on par with Arm's Cortex-A15 but it is half the size in terms of transistors while delivering similar performance. The proAtiv have a higher CoreMark at this point and it almost 75% faster than the 1074K Series. This means that a quad proAptiv system could challenge a dual Cortex-A15 design based on space or dual proAtiv would have space for a 1 Mbyte L2 cache.
Figure 2. The proAptive line supports up to six cores with a fused, triple-dispatch, super scalar, out-of-order (OoO) execution pipeline.
The proAtive fused, triple-dispatch, super scalar, out-of-order (OoO) execution pipeline (Fig 3). The wide issue instruction decode can feed up to four integer and two floating point operations per cycle. The floating point unit (FPU) design is new as well. The memory management unit has been improved including support for extended virtual addressing (EVA) that provides better address utilization. A fused load/store unit design doubles the bandwidth of the memory pipe. Like the overall core design, the smaller load/store units allow more units to be incorporated for better performance.
Figure 3. The proAptiv uses a fused, triple-dispatch, super scalar, out-of-order pipeline.
The Coherent Processing System (CPS) is based around the Enhanced Coherence Manager Gen 2 (CM2). The CM2 is used with proAptive as well as interAptiv cores. It will handle up to 4 interAptiv cores or 6 proAptiv cores per coherent cluster. The CM2 delivers a 2x latency improvement and doubles the system bandwidth compared to earlier designs. It supports up to an 8 Mbyte L2 cache.
In addition, it works with two I/O coherence unit (IOCU) providing consistent data when dealing with I/O transfers. The system supports up to 256 global interrupts. The PDtrace facility helps developers debug difficult timing related problems.
Advanced power management complements the performance advantages of the proAptvi. The design supports cluster power control as well as volt domain gating/core and clock gating/core.
The midrange interAptiv supports one to four cores. Like the proAptiv line, the interAptiv designs support ECC for on and off-chip memory. This includes the on-chip caches allowing the family to address the increasing number of safety targeted designs.
The interAptive 32-bit memory system supports over 3 Gbytes of user space. It also has extensive power management features similar to the proAptiv.
The microAptiv family is a single core design (Fig. 4). It targets single core microprocessor (MPU) as well as microcontroller (MCU) platforms. The microAptiv familty supports the microMIPS code compression instruction set with a simple memory addressing scheme.
Figure 4. The microAptiv targets single core microprocessor (MPU) as well as microcontroller (MCU) platforms.
The microAptiv line is designed for low power applications. It uses a highly efficient, 5-stage, in-order instruction pipeline with a 10-cycle interrupt latency. On-chip SRAM and cache are optional and will often be eliminated for low cost applications.
The familty supports an optional DSP mode with a dedicated DSP pipeline that allows the microAptiv to challenge Arm's Cortex-M4 DSP. This includes an 8/16-bit SIMD engine. The DSP support adds 159 DSP instructionsm, 70 SIMD instructions, and 38 multiply/accumulate (MAC) instructions. The DSP side has single cycle throughput and support for up to four accumulators.
The Aptiv line represents a radical marketing shift for MIPS but a more generational shift from an architectural standpoint. The overall MIPS architecture remains intact with performance and power management refinements. MIPS has had success in a number of areas but its main challenger remains Arm. Luckily the toolsets for both are comparable allowing designers to choose based on cost, power and performance where MIPS does very well.
