Developing advanced embedded systems is becoming more and more challenging to the designer. Functionality and connectivity create layers of added integration and complexity that often make it difficult to provide an optimum logic architecture to manage a given system, especially if it’s a system-on-chip (SoC). Let’s explore the anatomy of an embedded FPGA (eFPGA) and how to achieve the best optimization of silicon resources with the maximum amount of flexibility.
If we strip an FPGA into its component parts, we find primarily a core, typically containing the logic, memory, other macros such as DSP, an interconnect grid of wires, switches, and other compute elements, arranged in a grid or matrix. The I/O ring usually contains high-speed interfaces to the physical world, such as SerDes, LVDS, CMOS, and TTL interfaces. An eFPGA is, in essence, just the core of an FPGA without the I/O ring.