Cyclone V and Arria V FPGAs can include dual core Cortex-A9 processors
Altera has announced its 28nm Cyclone V and Arria V FPGA lines (Fig. 1) that will support dual core Arm MPCore Cortex-A9 processors. The hard core processors are surrounded by a set of typical microcontroller periherals in addition to high speed connections to the FPGA fabric. Altera is not the first to include ARM cores in an FPGA and most can incorporate soft core Arm processors. One feature that most solutions lack is ECC (error correcting code) that provides single bit error recovery. This is key to applications such as avionics and medical were hardware like this matters.
Altera includes a single hard core ECC memory controller with each dual core processing complex in addtion to a shared 512 Kbyte L2 cahce. Additional soft core memory controllers can be defined within the FPGA fabric to provide a higher memory performance for applications that require it. The QSPI (quad serial peripheral interface) support can also handle ECC. The system supports various boot modes including booting from QSPI.
Hard core Arm processors can be found in Microsemi's SmartFusion (see FPGA Combines Hard-Core Cortex-M3 And Analog Peripherals) that incorporates a hard core ARM Cortex-M3. The Cortex-M3 is found in a wide range of microcontrollers. Xilinx's Zynq-7000 EPP
Altera has also partnered with Intel to bring the Atom to Altera FPGAs (see Configurable Platform Blends FPGA With Atom). The difference with the E600C from Intel is that the Atom and Altera FPGA are separate chips combined on a multichip carrier. The two are linked via a pair of x1 PCI Express links via the multichip carrier. This is functionally similar to the Cortex-A9 approach but the new chips are true single chip solutions.
Altera's FPGAs can boot the micro or FPGA only and the processors can reprogram the FPGA fabric. The complement of peripherals includes a pair of gigabit Ethernet interfaces, two USB 2.0 OTG ports plus the usual timer and serial ports like SPI and I2C. The higher end Arria has a 125+ Gbit/s interconnect. The 250 MHz 256 bits full duplex channel is compatible with AMBA AXI 3 interface and it also supports Altera's Avalon bus. The system supports cache coherent hardware accelerators.
Performance is the name of the game with FPGAs. Off chip interface includes 10 Gbit/s SERDES and dual 2 PCI Express Gen 2 x4 links.
The system is very flexible. It can run a single core to reduce power consumption. It delivers 4000 DMIPS for under 1.8W per processor. The top end Arria with dual Cortex-A9s consumes only 15W.
Developers can take advange of the new chips using Altera's Quartus II software and Qsys system integration tool. Hardware is still in the future so 2012 is when developers will see quantities of these chips. In the meantime, Altera's SoC Virtual Target software is available now.
The development software is a full virtual model based on tools from Synopsys. Initially this is a full virtual model but in the near future Altera will be offering a hardware-in-the-loop solution. In this case, PCI Express will be used to link an Altera FPGA to a host PC running the simulation software. The Cortex-A9 hardware will be simulated on the PC. This may seem like a stopgap measure but it is more than that.
The FPGA has a small bit of custom IP to handle the PCI Express interface. This means, in the future, that almost any IP can be simulated. This is handy for existing designs since they can be linked to new virtual hardware with the new physical hardware replacing it when the design is complete.
The other advantage with a virtual model is the degree of exposure developers have to the processor cores. Arm has the usual debug and trace interfaces but these provide a limited look into the hardware. A simulator does not have the limitation. Developers have been taking advantage of this approach for other chips, not just FPGAs.
Altera's choice of Cortex-A9 cores opens their product line to the Arm community. It also follows the trend to centering FPGA designs around processor cores even if the cores are not doing the heavy lifting. It also makes the FPGA a more likely target for a single chip solution.
