The decision to change from a functional to a structural test methodology is a far-reaching one. Functional test vectors are meant to check for correct device functionality. Structural test vectors target manufacturing defects and attempt to ensure the manufacturing correctness of basic device structures such as wires, transistors, and gates.
Driven by short product life cycles, ever-increasing device complexity, and geometrically rising integration levels, today’s microelectronic designers also confront rising development cost, hard-to-test circuits, and a validation problem of huge proportion. In addition, increasing test cost threatens the growth of electronic systems.
When technology can easily integrate 100 million transistors in a complex microprocessor or use cores and synthesized logic in a quick design of a 20-million-transistor ASIC, the generation of test vectors becomes the largest single portion of the product-development cycle. Once measured in weeks, now man-years of test development are possible for a complex device.
To date, test-automation breakthroughs have not kept pace with those in design and manufacturing. However, that is rapidly changing as the following developments enable the use of structural test:
- Small scan area overhead (~3% in VLSI).
- Availability of electronic design automation (EDA) design-for-testability (DFT) tools.
- ATE optimized for structural test methods.
The goal of test is to ensure the required defect coverage. For that reason, the test set must be intelligently chosen and based upon the types of expected defects, and the physical design and fabrication process will determine the defects.
Today’s complex processes equate to complex defects. There are many more locations for opens and shorts in a line, and the smaller device geometries lend themselves to inductive and capacitive coupling defects (Figure 1). As we move to the 100-nm realm with more metal layers, increased metal aspect ratios, tighter pitches, lower transistor thresholds, and exotic dielectric materials, the incidence of coupling defects will increase. Bridging and opens/resistive opens will assume a larger percentage role in the defect distribution.
Structural Test Strategy
The solution is to adopt a structural approach to test. This means a rule set that is tool driven in the design process and, largely, looks transparent to the designer. The logic is converted to scan and built-in self-test (BIST) according to a strict rule set. Tools for test development match the rule set, the implementation of scan and BIST, and the needed manufacturing equipment.
To make structural test work, four related elements must be in place, linked to one another, and implemented correctly. A structural-test implementation with gaps in any of the elements probably will fail, resulting in product delays and possibly some serious market-share loss.
Comprehensive DFT Implementation and Rule Set
The first element of a comprehensive structural-test approach is a comprehensive DFT implementation and rule set. This means rules such as:
- Required fault coverage and the corresponding fault models.
- Percent scan in random logic.
- Percent scan in data paths.
- How to deal with feedback paths.
- Control of bus access to avoid contention.
- How to handle register arrays.
- BIST of memory elements.
- Number of scan chains.
- Control of the DFT vs. functional operation of the chip.
- Clocking schemes matching the (faults) defects, test equipment, and the latch or flip-flop design.
- Use of the EDA tools for checking the test coverage.
Selection of EDA Tools
The second key element is the selection of EDA tools for the DFT and associated fault models. This includes considering how the tools are used in the process and how the faults are simulated. Again, this must match the number of scan chains and the type of fault models that were defined.
Equipment for Production Test
The third key element is the equipment for production test that matches the chosen EDA tools, fault models, DFT implementation, and the corresponding rule set that follows from it. The equipment must match the number of scan chains, the timing accuracy, and the methods needed for the different tests and be optimized for structural test to give the best possible cost. For example, once it is decided that functional test vectors are not needed during structural test, a reduced pin-count device/DFT interface port is feasible, reducing the tester’s channel count and cost.
Manufacturing Process
The fourth and final key element is a manufacturing process that links the elements together. This is the selection of where, when, and what in the manufacturing process is tested to ensure coverage. At what temperatures are the tests done? Is there a supplemental simple functional test to act as a safety net?
Putting It All Together
To illustrate how these elements link together, let’s consider the selection of a scan cell as an example. There are many kinds of scan-cell designs, ranging from simple mux latches to very complex cells with transistor counts of 10 to more than 100.
Different cells have different clocking arrangements. Some cells cannot do a timing-controlled launch and capture to test a path for a timing-related fault. As a result, the scan-cell selection must take into account what type of fault models will be used.
The path delay model, the gate delay (transition delay) model, or no delay model will impact the cell selection. Once the models are known, the timing for a launch and capture can be direct clocks from the tester, or it can be generated from an internal clock generator.
Using the Right Fault Models
Using the right fault models is an important factor in ensuring high defect coverage. Extensive analysis of the 1997 Sematech S-121 study led to significant conclusions:
- A nearly perfect stuck-at fault coverage vector set is not sufficient to achieve reasonable defects per million levels.
- Overlapping defect detection must exist between the different fault models.
- Many defects were only caught with IDDQ tests.
- A more holistic approach, using multiple fault models, will yield better defect coverage vs. devoting all the test application time to vectors targeting stuck-at faults.
As we move into deep submicron processes, the efficacy of IDDQ for catching all the bridges may diminish due to the increased background leakage. Yet, since the value of resistance a bridge defect may have and the likelihood of causing a delay-related defect is on the increase, more attention must be paid to modeling this defect.
What About Analog?
Analog circuits are not amenable to structural test methods and often will require a small number of functional vectors in support of the analog test. Devices with a preponderance of digital logic with some analog still benefit from the adoption of structural test methods. The analog circuits may require a tester with specialized instrumentation for the mixed-signal portion and digital functional capability for handshaking between the analog and digital sections of the chip.
Distributed Test
Since a robust structural test regimen consumes a fair amount of tester time, it makes sense to look at developing a test-flow strategy that minimizes the number of expensive, full-function, mixed-signal testers. In this scenario, full-function testers are used most efficiently for bare bones, functional-test-only application times.
Figure 2 (right) shows a generalized legacy test flow where the full test suite typically is repeated at each socketing. Let’s consider the economic impact of distributing the tests across the multiple test socketings the devices will undergo in the flow.
With knowledge about the assembly and packaging costs for the device, plus the escape rates, a straightforward financial analysis on the replacement of full functional testers with lower-cost structural testers is possible.
Summary
Structural test requires four independent but interrelated pillars to ensure success. Each of these relies on the others, and gaps or shortcomings in one area demand that the test engineer backstop with traditional functional-based testing.
The equipment chosen for test then becomes a key enabler or, if not linked to the design attributes, a key limiter. The equipment must have the right features to meet the structural test requirements.
The Schlumberger DeFT Structural Test System was developed to support a distributed test strategy. It matches test to design tools, cells, processes, and flows (Figure 3, see right).
The four pillars of design methodology, EDA tools, test equipment, and manufacturing processes, when implemented in a holistic approach, can deliver better quality at a lower cost. Then the decision becomes one of the following:
- Do I invest in structural test, with the added overhead of comprehensive DFT, new EDA tools, rules, and a well-aligned manufacturing process?
- Do I continue to purchase faster and higher pin-count functional testers and add staffing to generate test programs while still struggling to find ways to catch the tail-end defects?
Given a legacy of successful functional test generation, this decision will not be easy for an organization to make. However, the only real choice may be when to convert to structural test. Make it work; use it to your advantage to beat your competition in time to market and time to quality.
About the Authors
Rudy Garcia is a strategic marketing manager at Schlumberger Semiconductor Solutions. During 24 years at the company, Mr. Garcia has held positions in applications, engineering management, and marketing. He is an IEEE member and active in test-related forums such as the International Test Conference and was chairman of the Virtual Socket Interface Alliance Test Development Group in 1998-99. Prior to joining Schlumberger, Mr. Garcia worked at Bell Laboratories. Schlumberger Semiconductor Solutions, 150 Baytech Dr., San Jose, CA 95134, 408-586-6531, e-mail: [email protected]
Wayne Needham retired as a principal engineer of test at Intel in 1998. During his 26 years at the company, he held positions in engineering and engineering management including product, design, and test engineering. The senior member of IEEE also was employed by Hewlett-Packard, Signetics, and Memorex. Mr. Needham earned a B.S.E.E. and an M.S.E.E. from San Jose State University. 480-545-8127, e-mail: [email protected]
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November 2001 |