Single Chip Packs In 100 VLIW Cores
Tilera Tile-Gx block diagram
Tilera's Tile-GX family packs in up to 100 1.5GHz, 64-bit, VLIW cores (Fig. 1) into a single chip. It ties these cores together with a 1 Tbit/s/node iMesh switching system providing access to four memory controllers, peripherals including PCI Express links and mPIPE. The mPIPE packet processing front end handles network data from a configurable system that handles dual 40 Gbit/s streams, eight 10 Gbit/s streams or thirty two 1 Gbit/s streams.
The Tile-Gx family targets a range of multicore applications from deep packet inspection to cloud application servers. The architecture incorporates a range of features such as hardware parititioning including TileDirect coherent I/O links directly to processing cores. The Zero-Overhead Linux (ZOL) support is ideal for data plane applications that require low overhead and real time scheduling. Developers can also use Tilera's Bare Metal Environment (BME) within this context as well. Tilera's approach allows control and data plane tasks to be done on the same chip with the designer deterimine how many cores are allocated to these tasks and how they interact with each other.
The Tile-Gx chips specifications are extensive:
- 16 to 100 1.0 to 1.5GHz general-purpose processor cores (tiles)
- 64-bit VLIW processors with a 64-bit instruction bundle
- Three-way pipeline with up to three instructions per cycle
- 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, 256 Kbyte L2 cache per tile
- Up to 750 billion operations per second (BOPS)
- Up to 200 Tbits/s of on-chip mesh interconnect
- Over 500 Gbits/s memory bandwidth with four 64-bit DDR3 controllers with ECC support
- 10 to 55W for typical applications
- Idle Tiles can be put into low-power sleep mode
- Power efficient inter-tile communications
- Up to eight 10Gbit Ethernet XAUI interfaces; two Interlaken interfaces
- Three Gen2 PCIe interfaces, each selectable as endpoint or root complex
- Three StreamIO ports, each providing up to 20Gbits/s throughput for Tile-to-Tile or FPGA interconnect
- Up to 32 Gbit Ethernet MAC interfaces
- Wire-speed mPIPE packet processing engine
- On-chip hardware encryption and compression(MiCA)
The VLIW cores provide DSP and SIMD support. The iMesh on-chip network consists of multiple serial interfaces that handle I/O, data transfers and cache information. The network operation is transparent to programmers. The Tile-Gx can be split into cache coherent, SMP computing islands that run standard operating systems such as Linux using Tilera's DDC (Dynamic Distributed Cache).
Developers utilize conventional compilers, IDEs and debuggers to run applications in a virtualized environment. Of course, Tilera also provides advanced debugging and profiling tools that take advantage of the hardware. These are tied together Tilera's Eclipse-based IDE,Multicore Development Environment (MDE). Tilera also provides load balancing drivers and high speed packet processing stacks.
- GCC compiler (C/C++)
- Advanced profiling and debugging designed for multicore programming
- Supports SMP Linux and virtualization
- TMC libraries for efficient inter-tile communication
- Run off-the-shelf C and C++ programs
- Standard multicore communication mechanisms
Tilera's l00 core chip represents a significant advance in multicore design. Developers can utilize familiar tools and operating systems like Linux while taking advantage of the Tile-Gx's partitioning and peripheral system. Tilera's chips have already found a home in network appliances that provide firewall, VPN, Intrusion Detection and Prevention (IDS/IPS), Unified Threat Management (UTM) and Deep Packet Inspection services as well as multimedia streaming and video post production. The 100 core chip comes in a 45mm by 45mm BGA package.
