Increase LVS verification productivity in early design cycles
Aug. 20, 2020
Target short isolation analysis and debugging on incomplete/immature blocks, macros, and chips.
Introducing Calibre nmLVS-Recon, which gives designers a systematic methodology for prioritizing and resolving high-impact circuit issues in early design stages. Learn more about the short isolation use model, with three built-in options for analyzing specific areas:
Targeted short isolation analysis and debugging on incomplete/immature blocks, macros, and chips during early design phases
Fast iterations of short isolation analysis and debugging, speeding up overall time to tapeout
Partition designs by layer type, layer groups, or net type to support error prioritization
The flyback topology is a versatile, widely used, switched-mode power-supply design with some interesting characteristics that brings performance and BOM advantages to many applications...
Stricter guidelines imposed by version 3 of the IEC standard for harmonic current emissions push designers to embrace power-factor-correction methodologies.
In order to properly evaluate, certify, and optimize the power infrastructure of devices, programmable power supplies and loads are vital tools in testing products, from low-power...
