Increase LVS verification productivity in early design cycles
Aug. 20, 2020
Target short isolation analysis and debugging on incomplete/immature blocks, macros, and chips.
Introducing Calibre nmLVS-Recon, which gives designers a systematic methodology for prioritizing and resolving high-impact circuit issues in early design stages. Learn more about the short isolation use model, with three built-in options for analyzing specific areas:
Targeted short isolation analysis and debugging on incomplete/immature blocks, macros, and chips during early design phases
Fast iterations of short isolation analysis and debugging, speeding up overall time to tapeout
Partition designs by layer type, layer groups, or net type to support error prioritization
The high-voltage CCE4511 interface IC has overvoltage detection, as well as high temperature and overcurrent protection, based on 0.18m HV-CMOS technology. Typical applications...
Advanced asset tracking applications, such as livestock monitoring, fleet management, and logistics, automatically capture current status information and position coordinates ...
