Clocks typically are the last thing we consider in audio design (see parts 1-3 of “Soundbar Design From Start To Finish”). In many cases, they’re the one thing that comes back to bite us. Ignoring the significance of the three main clocks in traditional audio systems can cause some devices to not play nicely with others.
The system/master clock (SMCK) typically has a sampling frequency of 128x, 256x, or 512x. This clock drives most of the digital audio processing and filtering within the audio signal chain. Analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and digital signal processors (DSPs) usually require it.
The bit clock (BCK) generally has a sample rate of 64x or 128x. It’s used in the PCM/I2S audio stream as a clock that separates each bit in the data stream. This is essential in 99% of I2S devices so the receiver can tell the difference between a string of zeros and a single zero.
The word clock (LRCK) is the heartbeat of any good audio system, and it should be equal to the sampling frequency. In most systems, when this clock is high, the left channel is being transmitted. When it is low, the right channel is being transmitted. By synchronizing all processing and conversion to this clock, you should have no issues with synchronization and jitter within your audio system.
In most systems, the system/master clock is the main clock generated. From there, dividers generate bit clock and word clock/LRCK. There are caveats, however. Some devices include a phase-locked loop (PLL) that can regenerate a local system/master clock or, in some cases, an even bit clock from a reference clock (such as LRCK or BCK). Bear in mind that audio PLLs bring some really great advantages, but at some cost.
On-chip PLLs make electromagnetic interference (EMI) and layout issues much easier to manage. Not having to route 24.576-MHz signals all over your printed-circuit board (PCB) is going to make your life much easier. But on the downside, audio performance occasionally can suffer as PLLs inherently introduce some jitter.
Keep an eye on high-frequency distortion because jitter affects higher frequencies first. Imagine moving the sampling point back and forth in time. Lower frequencies don’t change amplitude much if you move the sampling point, but higher frequencies may have significant differences in amplitude.
Power consumption also increases when using an on-chip PLL. This isn’t much of a concern in a line-powered application like home audio. If you expect to operate your audio system from a battery, though, it’s worth investigating.
Clock Generation
First, we start with a simple example (Fig. 1). If you’re working with a digital input such as Sony/Philips Digital Interconnect Format (S/PDIF), the receiver probably regenerates all clocks from the input stream by using its own integrated PLL to decode the S/PDIF into I2S. If this is the case, unless you’re using a sample rate converter (SRC) (more details later), treat the receiver as the system’s clock master. Now all other clocks and devices should sync to it.
1. Note the clock relationship in this simple block diagram of a S/PDIF receiver driving a processor and digital amplifier. The clocks for the entire system can be derived from the incoming S/PDIF stream.
In an analog inputs only system, you the designer must generate an internal master clock within your product. This master clock is used to drive the ADC, processor, and digital amplifier, if the digital amplifier requires I2S. Most designers in the industry generate these clocks using one of four methods:
- Direct digital synthesis (DDS) device: Some designs use a DDS device where a relatively inexpensive IC generates a very high-speed clock. PC motherboards use this type of clock generation. A DDS device can generate different rates on the fly. For example, it can generate the master clock for 44.1 kHz for one setting, then switch to 96-kHz mode in another setting.
- PLL circuit: Depending on the type of PLL (fixed multiple, or multiply and divide structure), different master clocks can be generated in manner that’s similar to DDS. PLLs require a known clock rate to multiply/divide from or to use as a reference. The reference can be a fixed-rate CMOS output oscillator or a Pierce oscillator.
- Fixed-rate CMOS output oscillators: Many designers buy an off-the-shelf CMOS oscillator for systems where the sampling rate is fixed. These simple devices tend to be very reliable. Just add a power supply (3.3 V and GND), pull up the “enable” pin, and you have a very clean master clock output at a fixed frequency. Semiconductor manufacturers often use these oscillators on evaluation boards and in systems that can afford the extra dollar or so.
- Pierce oscillator: Used more in consumer audio systems, a Pierce oscillator can be created using a simple crystal and a $0.10 piece of logic. The Pierce oscillator is by far the cheapest way to generate a master clock (Fig. 2). Again, these systems usually have a fixed clock rate. Some customers may use two different Pierce oscillator circuits because they are low cost, if the system needs to support 44.1 kHz (and multiples) and 48 kHz (and multiples: 96 kHz, 192 kHz).
2. Pierce oscillators are easy to design. But if you expect to support multiple sample frequencies, the solution size can increase.
Of course, nothing comes for free. While cheap in chip price, Pierce oscillators involve other costs such as board space and a higher number of components then CMOS oscillators. Also, the output clock from a Pierce oscillator doesn’t always have a perfect 50/50 duty cycle. It actually is closer to 52/48.
This doesn’t cause a problem in many systems because the digital circuitry most likely will be single-edge clocking, but it is something to consider. A Pierce oscillator generates a single clock source. From there, it needs to be divided down to BCK and LRCK, a task typically performed by the clock master in your product.
Many experienced designers may have had different experiences and may have additional advice with this next part, but this is what I have learned.
The ADC is the most critical part of any digital audio circuit. It’s also the part that’s most sensitive to jitter. If you mess up the analog-to-digital conversion, there’s little you can do to compensate for it in the digital domain. This is why the master clock is generated next to the ADC in many professional audio systems. The ADC is used in master-mode, which causes the ADC to divide down and distribute the SCK, BCK, and LRCK to the rest of the audio signal chain (Fig. 3).
In our example, where you have a digital input feeding a sample rate converter (SRC), the SRC behaves as a clock domain isolation barrier (Fig. 4). The DSP and amplification system need to run from its own clock source, which is shared with the SRC output side.
4. Designers can convert different clock rates to the system clock rate by using an SRC.
This type of system allows simple switching from analog inputs to digital inputs, as the data rate is synchronized from an ADC or SRC (S/PDIF source). This method is nice and easy. Without the SRC, the system must mute, clear the processing pipeline, switch the sample rate (bank switching), start running data through the new pipeline, and unmute.
One final note: never, ever try to transfer data from one system to another, such as going from a CD player S/PDIF output to a DAC input, without the slave side locked in to the transmitter (Fig. 5). In most systems, the DAC input slaves to the S/PDIF. If they don’t, users will have lots of noise issues with pops and clicks.
5. The difference in clock rates as box A and its own crystal transmits to box B with its own crystal will generate overruns and underruns in buffered audio memory, eventually causing pops and clicks.
You may have two crystals that say they are both 48 kHz, but that doesn’t mean they’re exactly the same. Any drift in specification causes the transmitter to generate data faster or slower than the receiver. This immediately causes buffer underruns or overruns, which cause lots of pops and clicks (bad for speakers) and potentially can crash your system.
There are ways around this, using buffers and generating interrupts once the receiving buffer is mostly empty or mostly full. However, that’s another article waiting to be written. Designers involved with USB/Firewire and other non-time-guaranteed protocols typically have lots of experience with this.
Our multi-SKU (end product from same design) strategy drives the need for multiple clock generation strategies. In the value soundbar reference design, we have two stuffing options for clock mastering. We use the DIR9001 S/PDIF receiver that, when locked, generates all clocks for us. When unlocked, it simply uses an onboard crystal with some dividers to generate an “analog mode” clock source (Fig. 6).
6. The DIR9001 circuit uses the CKSEL pin to select between the S/PDIF clock recovery outputs, and using the reference crystal to generate the clocks for the system. CKSEL can be connected to the S/PDIF lock pin on the device for auto switching.
For systems with digital inputs, the S/PDI receiver uses the crystal as a reference to calculate the sampling rate. When the S/PDIF is unlocked, the S/PDIF receiver (DIR9001) then generates the audio master clock for the system.
For analog-only systems, use the same crystal footprint to save PCB space. However, use an additional buffer in place of the DIR9001 to generate a fixed 24.576-MHz clock. This is divided down by the PCM3070 for use in its codecs and multiplied to a higher frequency (using a PLL) for use in the miniDSP. Doing so saves the cost between using the DIR9001 in analog systems and using a $0.10 crystal buffer in the systems.
Slowly but surely, we are getting to the end of component selection! In our next article, we will address how to select power supplies and power amplifiers. For more information about audio, visit www.ti.com/soundbar-ca.