NVM Express
Flash memory is intimately linked to microcontrollers but when it comes to large storage copacities USB flash drives and solid state disk (SSD) drives come to mind. The former places the USB interface between the microprocessor and external storage. The latter typically uses a SATA or SAS interface. In both cases, there is a level of hardware and software between the operating system and the storage device.
Normally the interface useful but with solid state storage the interface tends to be the bottleneck. PCI Express is typically the interface to a SATA or SAS interface so the question arises: why not use PCI Express. This is where the Non-Volatile Memory Host Controller Interface (NVMHCI) Work Group and the NVM Express (NVMe) standard comes in.
There have been a number of flash solutions connected by PCI Express like Fusion-io's ioDrive (see Smart Storage). These employ host managed flash and require a custom driver. This approach can simplify the flash controller on the board at the expense of a more complex driver.
The NVMe approach requires a more intelligent controller that handles features like load leveling. The advantage is a consistent interface and the ability to provide a generic device driver to handle any compatible board. Initially NVMe was designed for server environments. This has since been expanded to client and embedded applications.
The standard defines parallel operations using up to 64K queues and 64K commands/queue. There is also a queue priority mechanism. The standard targets block sizes commonly used. A 64 byte command is sufficient to define a 4Kbyte read request. The standard supports multiple namespaces and aggregation of MSI/MSI-X and interrupts. SR-IOV support is defined and can be included to support virtual server environments. This is not as useful for client environments.
Standard interfaces are defined for PCI Express boards as well as a 2.5-in form factor. The latter has a x4 PCI Express Gen 2 interface. The standard will eventually support PCI Express Gen 3.
