What you’ll learn:
- How smart devices should be designed for power efficiency.
- Design considerations for the next generation of IoT devices.
We’ve become more accustomed to the presence of smart devices in our home and expect them to become more intelligent, recognizing and interpreting voice and movement through advanced audio- and video-processing techniques as well as sophisticated sensors. But such advances, enabled through innovative artificial-intelligence (AI) and machine-learning algorithms, increase the demand for greater power efficiency in the devices and underlying chips on which they’re based.
In the chip design world, considerations for power are nothing new. Design engineers are constantly working to optimize for energy consumption targets, and “low power” has been a longstanding mantra—one of the three legs in the Holy Grail of performance, power, and area (PPA).
It’s already a tall order to support the existing capabilities of smart devices, including:
- Speakers with voice control that utilize highly accurate speech recognition from an extensive vocabulary of trained voice commands.
- Wearable activity trackers that recognize human activity such as sitting, standing, walking, and running based on input data from sensors like gyroscopes, accelerometers, and magnetometers.
- Smart camera-equipped doorbells, performing facial recognition and triggering an alert that can be sent to the owner’s mobile device with an image or video.
- Even self-driving cars, applying advanced computer-vision techniques to detect vehicles, pedestrians, and hazardous driving conditions.
But as we consider how applications like AI are driving the need for larger chips, this brings new dynamics to the power equation.
Tamp Down the Temp
All of this intelligence is being driven by advances in AI. But because AI requires increasingly high volumes of processing performance, the chips will continue to get bigger with more transistors and even more novel architectures such as 3D stacking. As they process more information faster, one of the key limitations for chip performance will be temperature. So many transistors on the same die results in high density, causing the junction temperature to go up and chip performance to start declining.
Designers will have to consider thermal runaway, since performance will essentially be limited by power. Indeed, electronic-design-automation (EDA) vendors are continuing to work on elevating temperature as one of the key targets that chips must address for successful operation, along with the familiar PPA balancing act.
While the need to manage power and temperature is critical in plugged-in devices, it becomes even more of a challenge with battery-powered Internet of Things (IoT) devices. For these devices, with their milliwatt power budgets, there’s no margin for error or negotiation when it comes to the energy consumed by their chips. On top of that, as chips for these applications move to ever-smaller process nodes—think 7, 5, or 3 nm—and to gate-all-around architectures, leakage is decreasing but is still a critical issue to manage. At lower-voltage operation, designers will need to look more carefully at variation across transistors as well as timing.
Enhancing Efficiency
All of this demands a power-efficient processor, as well as excellent cycle efficiency so that the IoT device’s processor can do its job within the intended application and use case. Low-power consumption and management are particularly important for IoT edge devices that perform always-on functions, such as smart speakers, smartphones, or home entertainment systems that have “always-listening” voice-command capabilities. The same is true for camera-based devices performing facial detection or gesture recognition, which are “always watching.” And our health and fitness monitoring devices must be “always sensing.”
Such devices typically apply smart techniques to dynamically reduce power consumption. For example, an always-listening device may sample the microphone signal and use simple voice-detection techniques to check if anyone is speaking at all. It then applies the more compute-intensive machine-learning inference for recognizing voice commands only when voice activity is detected.
A processor must limit power consumption in each of those different states—in this case, voice-detection and voice-command recognition. As a result, various power-management features, including effective sleep modes and power-down modes, must be utilized to meet energy-consumption requirements.
So how do engineers approach these challenges?
Applying Power-Management Tactics
Traditionally, the most important weapon of choice for reducing power has been clock gating, and it has evolved over the years from simple clock gating to self-gating to sequential clock gating. While dynamic voltage scaling (DVS) provides a fairly common power-reduction technique, many designs are now starting to move to the more advanced adaptive-voltage and frequency-scaling (AVFS) methodology.
For machine-learning inference with low to medium compute requirements (a large portion of consumer IoT devices), selecting the right processor is key to achieving the high efficiency needed. Specifically, having the right processor capabilities for neural-network processing can be the difference between meeting low megahertz requirements (and, thus, low-power consumption) or not.
The advent of more powerful neural networks and algorithms has allowed the evolution of machine-learning-powered devices that learn without being explicitly programmed. However, the promise of greater automation and intelligence that machine learning enables, particularly in consumer, edge, and battery-powered devices, means that the P for power in PPA rules supreme.