Future Memory Technology for the Terabit Era
(Editor's note: At the imec technology forum held July 8 in San Francisco in conjunction with SEMICON West, Jan Van Houdt, director of the flash memory program, discussed emerging memory technologies. Here, he provides a brief summary of his presentation)
In 1956, the IBM supercomputer had a hard drive of one ton with the “huge” capacity of 5 MB. Today, there are USB sticks of 64 GB—storing 60,000 songs and 10,000 pictures. This successful story started in 1967 when Kahng and Sze published their paper describing the floating gate non-volatile memory cell. And the story still goes on today with mobile applications demanding for faster, larger memories that use less energy and have a smaller footprint. How can we achieve this?
DRAM Is Running Out of Space—3D Is the Way Up
It is clear that DRAM memories are running out of possibilities for further scaling: the leakage increases; the capacitor should increase to keep the refresh time constant; and an ever larger aspect ratio capacitor is needed. You could say that DRAM is running out of space.
3D integration is a way to extend the roadmap for DRAM. Dies are stacked and are connected with through-silicon vias. In this way, you create so-called hybrid memory cubes. This concept enables large parallelism, increasing the bandwidth of your system. Also, some of the logic functions can be taken off the DRAM chip and be put on a separate logic chip. In this way, the process costs of the chip go down and you have a large design space. Notice that this solution is more performance than cost-driven.
Flash Is Running Out of Electrons—3D Is the Way Up
Flash memories are the fastest growing semiconductor market in history. In 2000, cellular phones boosted NOR flash to become a 100 billion dollar market. In 2005, multimedia applications caused a second boom with NAND flash being a 20 billion dollar market. But the technology is being scaled to its ultimate limits. Let’s illustrate this by simulating the number of electrons available in a flash cell for different nodes. For the 20nm node, we had 230 electrons available, for the 15nm node this is 70 electrons and when we jump to the 5nm node we only have 19 electrons available. “Captain, we are running out of electrons,” would Dr. Spock have said if flash was a Star Trek episode.
To create more space to be able to squeeze more electrons again 3D is the way to go. Die stacking—as is done in 3D DRAM – is not a good solution for flash memories. In the same way, stacking of planar layers is not a very cost-effective solution for 3D flash. The best way to go is stacking vertical cells in the so-called 3D SONOS technology. Next to an engineering challenge, this concept requires a thorough scalability study, channel characterization and modeling, and the evaluation of new materials for an improved channel.
Why Not Look at Completely Different Technologies?
The above was all about charge-based memories and 3D will definitely extend the roadmap for these. But why shouldn’t we also look to completely new technologies? You may have heard of them: FBRAM, PCM, MRAM/FRAM. These either did not make it or ended up in niche markets. However, there are two new technologies that are still considered to be feasible: STT-RAM and RRAM. STT-RAM is based on magnetic storage instead of electronic storage: Writing is done by switching the magnetization of the free magnetic layer. The current pulse is used directly through the magnetic tunnel junction. It is a possible successor for both DRAM and SRAM. The challenges on which researchers are working now are to scale down the STT element while maintaining the stack integrity and the thermal stability; a reduced programming current; and understanding of the failure modes. Resistive RAM (RRAM) on the other hand is a possible successor for flash memories. It has a large scaling potential since there is no electron count issue so dense arrays are possible and stacking is possible. Of course also this disruptive technology has many challenges: screen all the options; limit the variability; understand the basic mechanism and failure mechanisms; reduce the programming current; increase the resistive window and improve the retention at a low programming current.
With all these options—3D and new memory concepts—we believe that it is possible to pave the way to future memory technology for the Terabit era.
To learn all about vertical flash, spin torque magnetic RAM, resistive RAM and phase change memory and how it opens up new markets, visit www.itf2013-semi-us.be or http://www2.imec.be/be_en/about-imec/imec-technology-forums.html.