This article is part of TechXchange: RISC V
For those following the RISC-V space, SiFive's new Freedom E310 is a long-awaited milestone. For most, RISC-V is a relatively new notion.
In a nutshell, RISC-V is an instruction set architecture (ISA) that scales from 16-bit to 128-bit register platforms. The E310 is targets the Cortex-M0 space, but it can run at 320 MHz while sipping power—making it an interesting solution for the Internet of Things (IoT). The chip is available on the HiFive1 board (see figure) that has an Arduino form factor.
The HiFive1 Arduino-form factor board runs the SiFive E310 RISC-V chip.
The idea behind RISC-V is not new. MIPS and even ARM have RISC-like architectures. Issues like code density and ISA functionality have fallen by the wayside, making other factors more important when deciding whether to use RISC-V. The performance or power efficiency is more a function of the microarchitecture implementation rather than the choice of ISA. Much of the success of the x86 CISC architecture is due to the plethora of software and platforms like Microsoft Windows. Much of ARM’s popularity is due to Linux and platforms like Android that are built on it.
So what does RISC-V offer? Customization at a lower cost compared to Imagination Technologies, MIPS, and ARM that essentially live off of licensing fees. These costs are passed on for standard parts like those available from micro vendors like Microchip, Qualcomm, and Texas Instruments and amortized across millions of chips. The infrastructures surrounding these two architectures are part of the benefit of using them. Availability of developers familiar with the platforms is another.
This type of community is what the E310 is designed to inspire. Likewise, the use of the IP in FPGAs is another option. Microsemi is supporting RISC-V. This makes a lot of sense as its competitors, Altera and Xilinx, have their own soft core processors (NIOS and MicroBlaze, respectively). Of course, RISC-V is one that can span all the FPGA vendors. The Cortex-M0 and -M1 are another, licensable option.
Now, the E310 core IP is open-source, but not all RISC-V implementations will be. There is the open-source Rocket core IP generator, which provides a good implementation for free. However, it isn't necessarily optimized like many of the MIPS and ARM solutions, or those that the micro vendors utilize. Still, the Rocket solutions may be more than sufficient for many developers. There are open-source peripheral and accelerator IP that can be used to create a final system-on-chip.
One reason this alternative to MIPS and ARM is of interest in the IoT space are aspects like customization requirements and cost, which can be significant. Low power and performance are typically on the checkbox list, but RISC-V fits nicely with all these aspects. SiFive can deliver a customized version of the E310 for about $100,000. That is a lot less than many alternatives.
Going with a custom chip for IoT applications has many advantages, ranging from optimizing power and performance to incorporating custom peripherals. Custom chips make reverse-engineering more difficult. Of course, using open-source or low-cost hardware helps the bottom line.
While processor chip vendors might consider adding RISC-V platforms to their stable, I think that will unlikely given the infrastructure and community they have already built up. The migration to ARM or MIPS platforms has taken years, and anyone considering a change would need to take these issues into account.
Custom IoT designs can benefit from an existing infrastructure and community, but are not as beholden to them. Likewise, much of this infrastructure is generic, such as the use of Eclipse-based IDEs and standard compiler technologies.
RISC-V is certainly worth watching. It may well fit into your IoT plans.
